View 218S6ECLA13FG_3786823.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

technical reference manual rev. 3.05 p/n: 42119_sb600_ds_3.05 ? 2007-2008 advanced micro devices, inc. sb600 databook
trademarks amd, the amd arrow logo, athlon, and comb inations thereof, ati, ati logo, radeon, and crossfire are trademarks of advanced micr o devices, inc. hypertransport is a licensed trademark of the hypertransport technology consortium. microsoft and windows are registered trademarks of microsoft corporation. other product names used in this publication are for identificati on purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no repre sentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the ri ght to make changes to specifica tions and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. except as set forth in amd's standard term s and conditions of sale, amd assumes no li ability whatsoever, and disclaims any expr ess or implied warranty, relating to its products including, but not limited to, the imp lied warranty of merchantability, fitness for a particular purpo se, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could creat e a situation where personal injury, death, or severe property or environmental damage may occur. amd re serves the right to discontinue or make changes to its produ cts at any time without notice. ? 2007-2008 advanced micro devices, inc. all rights reserved.
?2007- 2008 advanced micro devices, inc. table of contents sb600 databook proprietary page 3 table of contents 1 introducti on ............................................................................................................. 7 1.1 features of the sb600.......................................................................................................... .......... 7 1.2 block diagram and system configur ation.................................................................................... 10 1.3 part number and branding....................................................................................................... .... 13 2 ball-out assi gnment ............................................................................................. 14 3 signal descri ption................................................................................................. 16 3.1 a-link express ii interface .................................................................................................... ....... 16 3.2 pci interface (pci host bus and internal pci/p ci bri dge) .......................................................... 16 3.3 ata66/100/133.................................................................................................................. ........... 17 3.4 lpc interface.................................................................................................................. .............. 18 3.5 usb interface .................................................................................................................. ............. 18 3.6 serial ata interface ........................................................................................................... .......... 18 3.7 power management / nort h bridge inte rface ............................................................................... 19 3.8 processor in terface............................................................................................................ ........... 23 3.9 smbus interface / general purpose open co llector .................................................................. 23 3.10 real time cloc k interface ...................................................................................................... ...... 24 3.11 reset / clocks / ate........................................................................................................... .......... 24 3.12 general pu rpose i/o............................................................................................................ ......... 24 3.13 external event / general event / general power management / general purpose open collector 26 3.14 ac ?97 link interface .......................................................................................................... .......... 28 3.15 hd audio in terface ............................................................................................................. .......... 28 3.16 xbus rom access interf ace...................................................................................................... .28 3.17 spi rom in terface.............................................................................................................. .......... 29 3.18 hardware monitor ............................................................................................................... .......... 29 3.19 power and ground............................................................................................................... ......... 30 3.20 pin st raps ..................................................................................................................... ................ 31 4 power planes and pin stat es ............................................................................... 34 4.1 power up and do wn sequ ences.................................................................................................. 34 power up/down sequ ence timing notes ............................................................................................ ................40 4.2 acpi timing.................................................................................................................... .............. 44 4.3 pull-up/-down requirements and integrated re sistors................................................................ 45 5 functional descr iption ......................................................................................... 52 5.1 ehci usb 2.0 and ohci usb 1.1 cont rollers ............................................................................. 52 5.1.1 usb architectu re over view...................................................................................................... ............52 5.1.2 usb power m anagemen t........................................................................................................... ..........53 5.2 smi#/sci g eneration ............................................................................................................ ....... 54 5.3 lpc isa bridge................................................................................................................. ............ 55 5.3.1 lpc interfac e over view ......................................................................................................... ..............55 5.3.2 lpc module bl ock dia gram ....................................................................................................... ..........58 5.4 real time clock ................................................................................................................ ........... 58 5.4.1 functional bl ocks of rtc....................................................................................................... ..............58 5.5 sata (serial ata) controller ................................................................................................... .... 59 5.6 ac ?97 co ntroller .............................................................................................................. ............ 60 5.6.1 output data str eam ............................................................................................................. ................61
?2007- 2008 advanced micro devices, inc. table of contents sb600 databook proprietary page 4 5.6.2 input data stream .............................................................................................................. ..................61 5.6.3 ac '97 controller-cod ec(s) conn ections......................................................................................... .....62 5.7 high definiti on audio .......................................................................................................... .......... 65 5.7.1 hd audio codec connecti ons..................................................................................................... .........65 5.7.2 hd audio and ac ?97 codec connecti ons in mixed co nfigurat ions .....................................................65 5.8 general events and gpios ....................................................................................................... ... 68 6 system clock sp ecificati ons................................................................................ 69 6.1 system clock descriptions...................................................................................................... ..... 69 6.2 system clock input freq uency specif ications ............................................................................. 69 6.3 system clock ac specifications ................................................................................................. .69 7 states of power rails during acpi s1 to s5 states ........................................... 73 8 electrical char acteristi cs ..................................................................................... 74 8.1 absolute maxi mum rati ngs....................................................................................................... ... 74 8.2 functional oper ating range..................................................................................................... .... 74 8.3 dc characte ristics............................................................................................................. ........... 75 8.4 rtc battery curren t consumption............................................................................................... 7 9 9 power require ments............................................................................................. 80 10 package info rmation ............................................................................................. 85 10.1 physical dimensions............................................................................................................ ......... 85 10.2 pressure spec ification......................................................................................................... ......... 86 11 thermal info rmation.............................................................................................. 87 12 testabilit y .............................................................................................................. 88 12.1 test contro l signals ........................................................................................................... .......... 88 12.2 xor chain te st mode ............................................................................................................ ..... 89 12.2.1 brief description of an xor chain .............................................................................................. .........89 12.2.2 description of the sb600 xor chain............................................................................................. ......90 12.2.2.1 unused pins .................................................................................................................... ......................................92 appendix a: pi n listing.............................................................................................. 93 appendix b: revisi on history.................................................................................. 105
?2007- 2008 advanced micro devices, inc. list of figures sb600 databook proprietary page 5 list of figures figure 1-1: sb600 block di agram................................................................................................ ................................10 figure 1-2: rs600/sb600/ddr2 ?marlin ? desktop system block di agram ............................................................. ....11 figure 1-3: rs600me-sb600-ddr2 ?albacor e? mobile system block di agram .........................................................1 2 figure 1-4: sb600 branding diagr am ............................................................................................. .............................13 figure 2-1: sb600 ball-ou t assignment (left) ................................................................................... ...........................14 figure 2-2: sb600 ball-ou t assignment (right) .................................................................................. .........................15 figure 3-1: str aps capt ure..................................................................................................... ......................................31 figure 4-1: sb600 power up/down sequence for platforms with intel proc essors ................................................... ..36 figure 4-2: sb600 s3/s0 power up/down s equence for platforms intel proc essors.................................................. 37 figure 4-3: sb600 power up/down sequence for platforms with amd proce ssors....................................................3 8 figure 4-4: sb600 s3/s0 power up/down sequence for platforms with amd pr ocesso rs .........................................39 figure 4-5: circuit for maintaining proper relationship betw een +v5_vref and vddq ............................................40 figure 4-6: pcie_pvdd vs. vdd ramp re quirement ................................................................................. ...............40 figure 4-7: timing for latching of straps ...................................................................................... ...............................41 figure 4-8: timing for sb pwrgd de-a sserted to rsm_rs t# de-a sserted ............................................................ .41 figure 4-9: dprstp# fully de-a sserted when sb pw rgd asse rted ................................................................... .....42 figure 4-10: cpu_stp# de-asse rted when sb pw rgd asse rted....................................................................... ......42 figure 4-11: glit ch on ld t_rst#................................................................................................ ................................43 figure 4-12: t13 m easurement points............................................................................................ .............................43 figure 5-1: sb600 usb 2.0 system blo ck diagr am................................................................................. ....................52 figure 5-2: a typica l lpc bus system ........................................................................................... .............................55 figure 5-3: lpc host controller interf aces and signals......................................................................... ......................56 figure 5-4: block diagr am of lp c modu le........................................................................................ ...........................58 figure 5-5: blo ck diagram of in ternal rtc ...................................................................................... ............................59 figure 5-6: blo ck diagram for t he sata mo dule .................................................................................. .......................60 figure 5-7: aclink ac_s dout serial stream...................................................................................... .....................61 figure 5-8: aclink acz_ sdin serial stream ...................................................................................... ......................62 figure 5-9: single ac ?97 codec co nnection..................................................................................... ..........................63 figure 5-10: multiple ac ?97 codec connec tion .................................................................................. ........................64 figure 5-11: hd audio codec conn ections ........................................................................................ .........................65 figure 5-12: hd audio and ac ?97 codec connections for mixed conf igurat ions .................................................... ...66 figure 5-13: schematic for hd a udio and ac ?97 codec connections in a mixe d configur ation ................................67 figure 6-1: timing labels for ac s pecifications of the sb600 clocks ............................................................ .............70 figure 10-1: sb600 23 mm x 23 mm 0.8 mm pitch 549-fcbga pa ckage out line* .....................................................85 figure 11-1 test mode c apturing sequ ence ti ming................................................................................ ....................89 figure 11-2: a gener ic xor chain............................................................................................... ...............................89 figure 11-3: on-chip xo r chain conn ectivity .................................................................................... .........................90
?2007- 2008 advanced micro devices, inc. list of tables sb600 databook proprietary page 6 list of tables table 1-1: sb600 part numbers .................................................................................................. ................................13 table 3-1: st andard st raps ..................................................................................................... .....................................31 table 3-2: de bug st raps ........................................................................................................ ......................................32 table 3-3: addi tional st raps ................................................................................................... ......................................33 table 4-1: sb600 power up /down sequenc e timing................................................................................. .................34 table 4-2: external resistor requ irements and integr ated pull up /down.......................................................... .........45 table 5-1: ehci support fo r power managem ent st ates............................................................................ .................53 table 5-2: ehci po wer state summary............................................................................................ ...........................53 table 5-3: causes of smi# and sc i.............................................................................................. ...............................54 table 5-4: lpc cycle li st and data direc tion ................................................................................... ...........................57 table 5-5: pi n defini tions ..................................................................................................... ........................................60 table 5-6: ac_sdout slots def initi ons .......................................................................................... ............................61 table 5-7: acz_sdin slots de finiti ons.......................................................................................... ..............................62 table 5-8: smi, sci, and wake event su pport by gpio and g eneral even t pins ..................................................... .68 table 5-9: functionality of the general events and gpios ac ross acpi states.................................................... ......68 table 6-1: sb600 syst em clock de scripti ons..................................................................................... .........................69 table 6-2: sb600 system clock i nput frequency s pecificat ions ................................................................... .............69 table 6-3: 14 mhz osc refer ence clock ac s pecificat ions ........................................................................ ..............70 table 6-4: 48mhz usb/sio clock ac spec ificat ions ............................................................................... ...................70 table 6-5: rtc x1 clo ck ac specif icati ons ...................................................................................... ..........................71 table 6-6: lpc clock ac specif icatio ns ......................................................................................... .............................71 table 6-7: pci clock ac specif icatio ns ......................................................................................... ..............................71 table 6-8: ac 97 clo ck ac specif icati ons ....................................................................................... ............................72 table 7-1: state of each power ra il during acpi s1 to s5 states ................................................................ ..............73 table 8-1: absolute maximum rating ............................................................................................. .............................74 table 8-2: dc characteristic fo r power supplies to the sb600 ................................................................... ................75 table 8-3: dc characteristics for interfaces on the sb600...................................................................... ....................75 table 8-4: gpio/gevent out put dc charac teristics............................................................................... ..................76 table 8-5: gpio/gevent i nput dc charac teristics................................................................................ ....................76 table 8-6: rtc battery current cons umption ..................................................................................... ........................79 table 9-1: configuration set up for sb600 power activity test .................................................................. ................80 table 9-2: power activity under confi guratio n 1 ................................................................................ ..........................81 table 9-3: power activity under configur ation 2 and 3 .......................................................................... ......................81 table 9-4: power activity under configur ation 4 and 5 .......................................................................... ......................82 table 9-5: power activity under configur ation 6 and 7 .......................................................................... ......................83 table 9-6: power activity for sb600 unde r a fully loaded syst em config uration .................................................. .....84 table 10-1: sb600 package physical di mensi ons .................................................................................. ....................85 table 11-1: sb600 thermal limits............................................................................................... ................................87 table 12-1: signals for the te st controller of the sb600 ....................................................................... ......................88 table 12-2: test mode si gnals .................................................................................................. ..................................88 table 12-3: test 0 bit s equence................................................................................................. ................................88 table 12-4: truth tabl e for an xo r chain ....................................................................................... ...........................89 table 12-5: list of pins on the sb600 xo r chain and t he order of connec tion.................................................... .....90 table 12-6: pins excluded from the xor chain ................................................................................... .......................92 table 12-7: sb600 pin list sorted by interface ................................................................................. ..........................93 table 12-8: sb600 pin list sorted by ball reference............................................................................ ......................99
?2007- 2008 advanced micro devices, inc. introduction sb600 databook proprietary page 7 1 introduction amd?s sb600 is a south bridge that integrates key i/o, communications, and audio features required in a state-of-the-art pc into a single device. it is specifical ly designed to operate with amd?s families of integrated graphics processors (igps) in desktop and mobile pcs. 1.1 features of the sb600 cpu interface ? supports the following intel processors: ? desktop: pentium 4, pentium d, pentium extreme edition, prescott, celeron, celeron d, cedar mill, presler, conroe, allendale ? mobile: mobile pentium 4, pentium m, mobile prescott, celeron m, yonah, yonah celeron, merom ? supports the following amd processors: ? desktop: athlon 64, athlon 64 fx, athlon 64 x2, sempron, opteron, dual-core opteron ? mobile: athlon xp-m, mobile athlon 64, turion 64, mobile sempron a-link express ii interface to the radeon igps ? 1/2/4-lane a-link express ii interface ? dynamic detection of lane configuration ? high data transfer bandwidth pci host bus controller ? supports pci rev. 2.3 specification ? supports pci bus at 33mhz ? supports up to 6 bus master devices ? supports 40-bit addressing ? supports interrupt steering for plug-n-play devices ? supports concurrent pci operations ? supports hiding of pci devices by bios/hardware ? supports spread spectrum usb controllers ? 5 ohci and 1 ehci host controllers to support 10 usb ports ? all 10 ports are usb 1.1 (?low speed?, ?full speed?) and 2.0 (?high speed?) compatible ? supports acpi s1~s5 ? supports legacy keyboard/mouse ? supports usb debug port ? supports port disable with individual control smbus controller ? smbus rev. 2.0 compliant ? support smbalert # signal / gpio interrupt controller ? supports ioapic/x-io apic mode for 24 channels of interrupts ? supports 8259 legacy mode for 15 interrupts ? supports programmable level/edge triggering on each channels ? supports serial interrupt on quiet and continuous modes dma controller ? two cascaded 8237 dma controllers ? supports pc/pci dma ? supports lpc dma ? supports type f dma lpc host bus controller ? supports lpc based super i/o and flash devices ? supports two master/dma devices
?2007- 2008 advanced micro devices, inc. introduction sb600 databook proprietary page 8 ? supports tpm version 1.1/1.2 devices for enhanced security ? supports spi devices up to 33mhz sata ii ahci controller ? supports four sata ports, complying with the sata 1.0a specification ? supports sata ii 3.0gbit/s phy, with backward compatibility with 1.5gbit/s ? supports raid striping (raid 0) across all 4 ports ? supports raid mirroring (raid 1) across all 4 ports ? supports raid 10 (4 ports needed) ? supports both ahci mode and ide mode ? supports ncq ? supports hot plug in ahci mode only ? supports advanced power management with ahci mode ? supports sata port multiplier (only for asic revision a13 and above. the total number of sata raid drives connected directly to the host and behind the port multiplier should not exceed 4 drives.) note: the sb600 does not support esata configuration directly from the host controller. ide controller ? single pata channel support ? supports pio, multi-word dma, and ultra dma 33/66/100/133 modes ? 32x32byte buffers on each channel for buffering ? swap bay support by tri-state ide signals ? supports message signaled interrupt (msi) ? integrated ide series resistors ac link interface ? supports for both audio and modem codecs ? compliant with ac-97 codec rev. 2.3 ? 6/8 channel support on audio codec ? multiple functions for audio and modem codec operations ? bus master logic ? supports up to 3 codecs simultaneously ? supports spdif output ? separate bus from the hd audio hd audio ? 4 independent output streams (dma) ? 4 independent input streams (dma) ? up to 16 channels of audio output per stream ? supports up to 4 codecs ? up to 192khz sample rate ? up to 32-bit per sample ? message signaled interrupt (msi) capability ? 64-bit addressing capability for msi ? 64-bit addressing ca pability for dma bus master ? unified audio architectu re (uaa) compatible ? hd audio registers c an be located anywhere in the 64-bit address space timers ? 8254-compatible timer ? microsoft high precision event timer (hpet) ? acpi power management timer rtc (real time clock) ? 256-byte battery-backed cmos ram ? hardware supported century rollover ? rtc battery monitoring feature power management ? acpi specification 2.0 compliant power management schemes ? supports c2, c3, c4 ? support c1e and c3 pop-up (amd platform only) ? supports s0, s1, s2, s3, s4, and s5 note: the sb600 only supports the acpi scheme. apm is not supported. ? wakeup events for s1, s2, s3, s4/s5 generated by: ? any gevent pin
?2007- 2008 advanced micro devices, inc. introduction sb600 databook proprietary page 9 ? any gpm pin ? usb ? power button ? internal rtc wakeup ? smi# event ? supports speedstep? ? full support for on-now? ? supports cpu smm, generating smi# signal upon power management events ? gpio supports on external wake up events ? supports clkrun# on pci power management ? provides clock generator and cpu stpclk# control ? hardware monitoring support ? support for asf hardware monitor ? supports 3 independent fan control outputs ? supports 1 amdsi function note: sb600 does not support thermal diode temperature sensing function.
?2007- 2008 advanced micro devices, inc. introduction sb600 databook proprietary page 10 1.2 block diagram and system configuration xbus figure 1-1: sb600 block diagram figure 1-1 is a block diagram for the sb600. figure 1-2 and figure 1-3 are configuration diagrams for sample systems utilizing a radeon igp and the sb 600. these sample systems do not necessarily demonstrate all features of the sb600. please refer to section 1.1 , features of the sb600 , for the full feature list of the device.
?2007- 2008 advanced micro devices, inc. introduction sb600 databook proprietary page 11 figure 1-2: rs600/sb600/ddr2 ?marli n? desktop system block diagram
?2007- 2008 advanced micro devices, inc. introduction sb600 databook proprietary page 12 figure 1-3: rs600me-sb600-ddr2 ?albaco re? mobile system block diagram
?2007- 2008 advanced micro devices, inc. introduction sb600 databook proprietary page 13 1.3 part number and branding o ggggg note 3 note 2 yyw w xxv note 4 note 1 218s6eala21fg taiwan note 5 sb600 note 1: pre-production marketing name note 2: amd branded part number (see table below) note 3: wafer foundry?s lot id and wafer id: gggggg = lot id; wxx = wafer id note 4: yy-assembly start year, ww-ass embly start week, xx- assembly location note 5: country of origin figure 1-4: sb600 branding diagram table 1-1: sb600 part numbers amd part number asic revision substrate revision lead free a12 c 218s6ecla12fg a13 c 218S6ECLA13FG a21 c 218s6ecla21fg
?2007- 2008 advanced micro devices, inc. ball-out assignment sb600 databook proprietary page 14 2 ball-out assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a *note* s5_3.3v_ 1 pci_pme #/geven t4# llb#/gpi o66 slp_s5# usb_oc 4#/gpm4 # s5_3.3v_ 2 usb_oc 0#/gpm0 # avddrx _0 usb_ate st0 usb_ate st1 avddc avssc usb_rc omp b vss_5 ri#/exte vnt0# sus_sta t# usb_oc 6#/geve nt6# pwr_go od usb_oc 5#/ddr3 _rst#/g vss_6 usb_oc 1#/gpm1 # avddtx_ 0 avddrx _1 avddtx_ 1 avddrx _2 avddtx_ 2 avddrx _3 c x2 blink/g pm6# scl1/gp oc2# usb_oc 7#/geve nt7# usb_oc 8#/az_d ock_rs usb_oc 9#/slp_s 2/gpm9# usb_oc 2#/gpm2 # usb_oc 3#/gpm3 # avss_u sb_2 avss_u sb_3 avss_u sb_4 avss_u sb_5 avss_u sb_6 avss_u sb_7 d rtc_gn d x1 rtcclk nc7 vss_11 lpc_pm e#/geve nt3# s3_stat e/geven t5# avss_u sb_13 usb_hs dm8- usb_hs dm7- e vbat rsmrst # pwr_bt n# wake#/g event8# test1 avss_u sb_15 usb_hs dp8+ usb_hs dp7+ f s5_3.3v_ 3 vss_13 sda1/gp oc3# sys_re set#/gp m7# rtc_irq #/gpio69 slp_s3# test2 avss_u sb_17 avss_u sb_18 avss_u sb_19 g vss_15 spi_hol d#/gpio 31 spi_clk/ gpio47 s5_1.2v_ 1 rom_rs t#/gpio1 4 spi_cs#/ gpio32 smbale rt#/thr mtrip#/ test0 avss_u sb_24 usb_hs dm9- usb_hs dp6+ h s5_1.2v_ 2 s5_1.2v_ 3 s5_1.2v_ 4 avss_u sb_26 usb_hs dp9+ usb_hs dm6- j vss_16 acz_sdi n1/gpio 43 spi_di/g pio12 acz_sdi n2/gpio 44 s5_3.3v_ 4 spi_do/ gpio11 s5_3.3v_ 5 vss_17 avss_u sb_28 avss_u sb_29 avss_u sb_30 k s5_3.3v_ 6 az_sdin 3/gpio46 az_rst# l ac_bitc lk/gpio3 8 ac_sdo ut/gpio 39 az_sync acz_sdi n0/gpio 42 ac_rst# /gpio45 vss_18 vin1/gpi o54 vss_19 vddq_5 m avss az_sdo ut ac_syn c/gpio4 0 fanout 0/gpio3 vddq_7 vin4/gpi o57 vin6/gpi o59 vin2/gpi o55 vss_20 vss_21 vdd_1 vss_22 n avdd az_bitc lk fanin0/g pio50 vdd_3 vss_24 vdd_4 p vss_26 fanin1/g pio51 vddq_8 vin5/gpi o58 temp_c omm vss_27 tempin0/ gpio61 tempin1/ gpio62 vddq_9 r vss_29 vdd_6 vss_30 t spdif_o ut/pcicl k7/gpio4 pciclk1 fanout 1/gpio48 nc6 vddq_10 vss_32 tempin3/ talert# /gpio64 tempin2/ gpio63 vss_33 u pciclk2 pciclk0 pciclk5 vdd_8 vss_34 vdd_9 v pciclk6 pciclk3 vss_36 fanout 2/gpio49 vin0/gpi o53 vin3/gpi o56 vin7/gpi o60 vss_37 vddq_11 vss_38 vdd_11 vss_39 w vss_42 vddq_12 pciclk4 fanin2/g pio52 ad3/rom a15 vddq_13 ad0/rom a18 ad2/rom a16 vss_43 y ad1/rom a17 stop# ad5/rom a13 aa trdy#/r omoe# frame# ad16/ro md0 nc5 ad4/rom a14 ad6/rom a12 ad8/rom a9 vss_45 vddq_16 vss_46 ab ad18/ro md2 ad20/ro md4 ad22/ro md6 cbe0#/r oma10 ad13/ro ma4 gnt3#/g pio72 avss_sa ta_1 ac ad24 ad26 ad9/rom a8 vddq_19 ad7/rom a11 vss_48 ad10/ro ma7 ad15/ro ma2 serr# sata_ac t#/gpio6 7 avss_sa ta_4 ad ad30 ad28 inte#/gp io33 ad12/ro ma5 nc3 vss_50 gnt0# avss_sa ta_7 pllvdd_ sata_1 ae vddq_22 req1# vss_52 ad14/ro ma3 nc4 vddq_23 v5_vref avss_sa ta_10 avdd_s ata_1 af intf#/gp io34 gnt1# inth#/gp io36 intg#/g pio35 lock# par/ro ma19 cbe1#/r oma1 avss_sa ta_12 sata_ca l avss_sa ta_13 ag ad31 ad29 cbe3# gnt4#/g pio73 irdy# vss_54 clkrun # perr# req2# a_rst# avss_sa ta_16 avss_sa ta_17 avss_sa ta_18 avss_sa ta_19 ah ad27 ad25 ad23/ro md7 ad19/ro md3 req4#/g pio71 devsel# /roma0 gnt2# req3#/g pio70 cpu_stp #/dpslp _3v# avss_sa ta_26 sata_tx 3- sata_rx 3- sata_tx 2+ sata_tx 2- aj vss_55 vddq_26 ad21/ro md5 ad17/ro md1 cbe2#/r omwe# vddq_27 ad11/ro ma6 req0# pcirst# pllvdd_ sata_2 sata_tx 3+ avdd_s ata_11 sata_rx 3+ avdd_s ata_12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 figure 2-1: sb600 ball-out assignment (left) *note: for asic a11, there is a vss_1 ball at the a1 position. but for subsequent asic revisions, no ball exists there. however, references to the vss_1 ball may continue to exist in amd's reference schematics and other documents for the sb600, due to backward compatibility requirement with the sb460, which has a gr ound ball at the position. those references can be safely igno red for any sb600 motherboard design that does not also support the sb460. see the product advisory titled sb600 ball-out change notice (an_ixp600aa1) for details.
?2007- 2008 advanced micro devices, inc. ball-out assignment sb600 databook proprietary page 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 avss_u sb_1 usbclk usb_phy_1 .2v_1 usb_p hy_1.2 v2 vss_2 vss_3 avddck _1.2v wd_pwr gd/gpio 7 avddck _3.3v vddq_1 rom_cs #/gpio1 ssmuxse l/sata_is 3#/gpio0 vddq_2 vss_4 a avddtx _3 avddrx _4 avddtx_4 usb_p hy_1.2 v_3 usb_ph y_1.2v_4 usb_ph y_1.2v_5 avssck 14m_os c dpslp_ od#/gpi o37 vss_7 spkr/gp io2 smartvo lt/sata_i s2#/gpio4 sda0/gp oc1# ghi#/sat a_is1#/g pio6 b avss_u sb_8 avss_u sb_9 avss_usb _10 avss_ usb_1 1 avss_u sb_12 vss_8 vss_9 lan_rst #/gpio13 vss_10 lpc_smi #/extev nt1# ddc1_s da/gpio 8 scl0/gp oc0# sata_is 0#/gpio1 0 vddq_3 c usb_hs dp5+ usb_hsdp 4+ usb_h sdp1+ avss_u sb_14 shutdown #/gpio5/sm artvo lt2 vddq_4 ddc1_s cl/gpio 9 pcie_vs s_1 pcie_vs s_2 pcie_vs s_3 d usb_hs dm5- usb_hsdm 4- usb_h sdm1- avss_u sb_16 nc1 vss_12 pcie_ca li pcie_ca lrn pcie_ca lrp e avss_u sb_20 avss_usb _21 avss_ usb_2 2 avss_u sb_23 vss_14 pcie_vs s_4 pcie_vd dr_1 pcie_vd dr_2 pcie_vd dr_3 f usb_hs dp3+ usb_hsdp 2+ usb_h sdp0+ avss_u sb_25 pcie_vs s_5 pcie_vs s_6 pcie_vs s_7 pcie_vd dr_4 pcie_vd dr_5 pcie_vd dr_6 pcie_vd dr_7 g usb_hs dm3- usb_hsdm 2- usb_h sdm0- avss_u sb_27 pcie_vs s_8 pcie_tx 3n pcie_tx 3p h avss_u sb_31 avss_usb _32 avss_ usb_3 3 pcie_vs s_9 pcie_rc lkp pcie_rc lkn pcie_vs s_10 pcie_vd dr_8 pcie_vs s_11 pcie_vd dr_9 j pcie_vs s_12 pcie_tx 2n pcie_tx 2p k vddq_6 pcie_vs s_13 pcie_vs s_14 pcie_vs s_15 pcie_vd dr_10 pcie_vd dr_11 pcie_vs s_16 pcie_vs s_17 pcie_vd dr_12 l vdd_2 vss_23 pcie_vs s_18 pcie_rx 3p pcie_rx 3n pcie_vs s_19 pcie_rx 2p pcie_rx 2n pcie_vs s_20 pcie_tx 1n pcie_tx 1p m vss_25 vdd_5 pcie_vs s_21 pcie_vs s_22 pcie_vd dr_13 n vss_28 pcie_vs s_23 pcie_vs s_24 pcie_vs s_25 pcie_vs s_26 pcie_vs s_27 pcie_vs s_28 pcie_tx 0n pcie_tx 0p p vdd_7 vss_31 r pcie_vs s_29 pcie_rx 1p pcie_rx 1n pcie_vs s_30 pcie_rx 0p pcie_rx 0n pcie_vs s_31 pcie_vs s_32 pcie_vs s_33 t vss_35 vdd_10 pcie_vs s_34 pcie_pv ss pcie_pv dd u vdd_12 vss_40 vss_41 pcie_vs s_35 pcie_vs s_36 pcie_vs s_37 pcie_vs s_38 pcie_vs s_39 pcie_vs s_40 pcie_vs s_41 pcie_vs s_42 v vddq_14 bmreq#/ req5#/g pio65 dprslp vr nmi/lint 1 init# intr/lin t0 ide_cs3 # ide_cs1 # vddq_15 w ferr# ide_a2 vss_44 y vddq_17 vss_47 vddq _18 ignne#/ sic slp#/ld t_stp# smi# stpclk# /allow_ ldtstp a20m#/si d cpu_pw r ide_irq ide_a0 aa avss_sa ta_2 avss_sat a_3 nc8 ide_a1 ide_dac k# ide_ior dy ab xtlvdd_ sata avss_sat a_5 avss_ sata_ 6 nc2 vddq_20 vss_49 ldt_rst #/dprst p#/proc cpu_pg/ ldt_pg ide_drq ide_iow # ide_ior# ac sata_x1 sata_x2 avss_ sata_ 8 avss_sa ta_9 vss_51 ide_d14/ gpio29 ide_d1/g pio16 vddq_21 ide_d0/g pio15 ide_d15/ gpio30 ad avdd_s ata_2 avdd_sat a_3 avdd_ sata_ 4 avss_sa ta_11 vddq_24 vss_53 ide_d13/ gpio28 ide_d2/g pio17 ae avss_sa ta_14 avss_sat a_15 avdd_ sata_ 5 avdd_s ata_6 serirq lframe# ga20in ide_d3/g pio18 ide_d11/ gpio26 ide_d12/ gpio27 af avss_sa ta_20 avss_sa ta_21 avss_sat a_22 avss_ sata_ 23 avss_sa ta_24 avss_sa ta_25 avdd_s ata_7 avdd_s ata_8 lad0 lad1 kbrst# ide_d9/g pio24 ide_d10/ gpio25 ide_d4/g pio19 ag sata_rx 2- sata_rx 1- sata_tx1+ avss_ sata_ 27 sata_rx 0- sata_tx 0+ avdd_s ata_9 avdd_s ata_10 lad2 lad3 ldrq1#/ gnt5#/g pio68 ide_d8/g pio23 ide_d5/g pio20 vddq_25 ah sata_rx 2+ sata_rx 1+ sata_tx1- avdd_ sata_ 13 sata_rx 0+ sata_tx 0- avdd_s ata_14 avdd_s ata_15 ldrq0# vss_56 vddq_28 ide_d7/g pio22 ide_d6/g pio21 vss_57 aj 16 17 18 19 20 21 22 23 24 25 26 27 28 29 figure 2-2: sb600 ball-out assignment (right)
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 16 3 signal description notes: 1. in the descriptions below, ?[intel]? indicates that the functions or descriptions apply only to intel platforms and ?[amd]? indicates that they only apply to amd platforms. 2. for acpi timing details, refer to se ction 4.2, ?acpi timing for the sb600.? 3. for multi-function pins, go to the relevant sectio n for description of the relevant function (e.g., for smalert#/thrmtrip#/gevent2#, the sm bus alert function is described in section 3.9, ?smbus interface / general purpose open collector? and the thermal tr ip function is described in section 3.7, ? power management / north bridge interface ?). 3.1 a-link express ii interface pin name type voltage functional description pcie_tx[3:0]p o a-link express ii lane 3-0 transmit positive pcie_tx[3:0]n o a-link expr ess ii lane 3-0 transmit negative pcie_rx[3:0]p i a-link express ii lane 3-0 receive positive pcie_rx[3:0]n i a-link express ii lane 3-0 receive negative pcie_rclkp i a-link express ii reference clock positive pcie_rclkn i a-link express ii reference clock negative pcie_calrp o a-link express ii calib ration, tx termination reference resistor connection pcie_calrn o a-link express ii calibra tion, rx termi nation reference resistor connection pcie_cali i 1.2v (filtered) reserved. requires a pull-down to gnd. 3.2 pci interface (pci host bus and internal pci/pci bridge) pin name type voltage functional description ad[15:0]/roma[18:11, 9:2] i/o 3.3v (5v tolerance) pci bus address/da ta [15:0] / rom address [18:11, 9:2] ad[23:16]/romd[7:0] i/o 3.3v (5v tolerance) pci bus address/data [23:16] / rom data [7:0] ad[31:24] i/o 3.3v (5v tolerance) pci bus address/data [31:24] bmreq#/req5#/gpio 65 i/o 3.3v (5v tolerance) bus master req# (p4/k8) / pci request 5 input / gpio 65 cbe0#/roma10 i/o 3.3v (5v tolerance) co mmand/byte enable[0]/ rom address [10] cbe1#/roma1 i/o 3.3v (5v tolerance) co mmand/byte enable[1]/ rom address [1] cbe2#/romwe# i/o 3.3v (5v tolerance) command/byte enable[2]/ rom we # cbe3# i/o 3.3v (5v tolerance) command/byte enable[3] clkrun# i/o 3.3v (5v tolerance) clock running is de-asserted by the clock provider to indicate the system is about to shut down the pci clock. when it is driven low by other agents, it means the agent is requesting the clock provider to not deactivate the clock. devsel#/roma0 i/o 3.3v (5v tolerance) device select / rom address [0] device select: driven by target to indicate it has decoded its address as the target of the current access. frame# i/o 3.3v (5v tolerance) cycle frame: driven by the current master to indicate the beginning and duration of an access. gnt#[2:0] o 3.3v (5v tolerance) pci bus grant [2:0] from the sb600: indicates to the agent that access to the bus has been granted. gnt3#/gpio72 o 3.3v (5v tolerance) pci bus grant 3 from sb600 / gpio 72
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 17 pin name type voltage functional description gnt4#/gpio73 i/o 3.3v (5v tolerance) pci bus grant 4 from sb600 / gpio 73 int[h:e]#/gpio[36:33] i/o 3.3v (5v toleranc e) pci interrupt [h:e] / gpio [36:33] irdy# i/o 3.3v (5v tolerance) initiator ready: indicates the initiating agent?s ability to complete the current data phase of the transaction ldrq1#/gnt5#/gpio6 8 i/o 3.3v (5v tolerance) encoded dma/bus master request 1 / pci bus grant 5 from sb600 /gpio 68 lock# i/od 3.3v (5v tolerance) pci bus lock par/roma[19] i/o 3.3v (5v tolerance) pci bus parity / rom address[19] pciclk[4:0] o 3.3v (5v tolerance) 33 mhz pci clocks [4:0] pciclk5 o 3.3v (5v tolerance) 33 mhz pci clock 5 / lpc clk 0 pciclk6 o 3.3v (5v tolerance) 33 mhz pci clock 6 / lpc clk 1 pcirst# o 3.3v (5v tolerance) hardware reset for pci slots assertion: (a) at power on, (b ) sometime after cpu_stp#?s assertion in s0, (c) after the system has transitioned into s4/s5. de-assertion: sometime after sb pwr_good is asserted during power on or during a transition from s4/s5 to s0. perr# i/o 3.3v (5v tolerance) parity error: reports data pa rity errors during all pci transactions, except in a special cycle. req#[2:0] i 3.3v (5v tolerance) request [2:0] input: in dicates that the agent desires use of the bus. req3#/gpio70 i 3.3v (5v tolerance) pci request 3 input / gpio 70 req4#/gpio71 i 3.3v (5v tolerance) pci request 4 input / gpio 71 serr# i/od 3.3v (5v tolerance) system error: for reporting address parity errors and data parity errors on the special cycle command, or any other system error where the result will be catastrophic. spdif_out/pciclk7/gpi o41 i/o 3.3v (5v tolerance) spdif serial out / 33 mhz pci clock 7 / gpio 41 stop# i/o 3.3v (5v tolerance) stop: indicates the current target is requesting the master to stop the current transaction trdy#/romoe# i/o 3.3v (5v tolerance) target ready / rom oe# target ready: indicates the target agent?s ability to complete the current data phase of the transaction. 3.3 ata66/100/133 pin name type voltage functional description ide_iordy i 3.3v (5v tolerance) ide io ready ide_irq i 3.3v (5v toleranc e) ide interrupt request ide_a0 o 3.3v (5v tolerance) ide address bus bit 0 ide_a1 o 3.3v (5v tolerance) ide address bus bit 1 ide_a2 o 3.3v (5v tolerance) ide address bus bit 2 ide_dack# o 3.3v (5v tolerance) ide dma ack ide_drq i 3.3v (5v tolerance) ide dma request ide_ior# o 3.3v (5v tolerance) ide io read ide_iow# o 3.3v (5v tolerance) ide io write ide_cs1# o 3.3v (5v tolerance) ide chip select for i/o 1xxh address ide_cs3# o 3.3v (5v tolerance) ide chip select for i/o 3xxh address ide_d[15:0]/gpio[30:1 5] i/o 3.3v (5v tolerance) ide data bus bit [15:0] / gpio [30:15]
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 18 3.4 lpc interface pin name type voltage functional description ga20in i 3.3v (5v tolerance) a20 gate input from sio kbrst# i 3.3v (5v tolerance) keyboard reset# lad[3:0] i/o 3.3v (5v tolerance) mu ltiplexed command/ad dress/data [3:0] lframe# o 3.3v (5v tolerance) frame. indicates start of a new cycle or termination of broken cycle. ldrq0# i 3.3v (5v tolerance) encoded dma/bus master request 0 ldrq1#/gnt5#/gpio6 8 i/o 3.3v (5v tolerance) encoded dma/bus master request 1 / pci bus grant 5 from sb600 / gpio 68 lpc_smi#/extevnt1# i 3.3v (5v tolerance) lpc smi / external event 1 serirq i/o 3.3v (5v tolerance) serial irq 3.5 usb interface pin name type voltage functional description usb_hsdp[9:0]+ i/o avdd_tx usb port 9 ~ 0 positive i/o. see note . usb_hsdm[9:0]- i/o avdd_tx usb port 9 ~ 0 negative i/o usbclk i avddc 48mhz clock used for usb usb_rcomp i avddc compensating resistors input usb_atest1 i/o avdd_tx ate test pin 1 usb_atest0 i/o avdd_tx ate test pin 0 usb_oc[4:0[#/gpm[4: 0]# i/o s5_3.3v usb over current [4:0] / gpm [4:0] usb_oc5#/ddr3_rs t#/gpm5# i/o s5_3.3v usb over current 5 / ddr3 memory reset / gpm 5 usb_oc[7:6]#/ gevent[7:6]# i/o s5_3.3v usb over current [7:6] / general event [7:6] usb_oc8#/az_dock _rst#/gpm8# i/o s5_3.3v usb over current 8 / hd audio dock reset / gpm 8 usb_oc9#/slp_s2/g pm9# i/o s5_3.3v usb over current 9 / sleep s2 indicator / gpm 9 note: the usb_hsdp[9:0]+ and usb_hsdm[9:0]- signals are normally connected to the usb port connectors, in which case the usb ports are often handled by hand and the associated devices, connectors, or even the signal pins are subject directly to esd events. the usb_hsdp+ an d usb_hsdm- signals that may be exposed to the user through an usb port connection must have esd protection. please refer to the product advisory pa_sb600au1 posted on the orc for further deta ils on esd device specifications. 3.6 serial ata interface pin name type voltage functional description sata_act#/gpio67 od 3.3v sata channel active / gpio 67 sata_cal i 1.2v (filtered) sata calibration sata_rx[3:0] - i 1.2v (filtered) sat a channel[3:0] receive negative sata_rx[3:0] + i 1.2v (filtered) sat a channel[3:0] receive positive sata_tx[3:0] - o 1.2v (filtered) sata channel[3:0] transmit negative sata_tx[3:0] + o 1.2v (filtered) sata channel[3:0] transmit positive sata_x1 i 3.3v (filtered) sata clock/crystal input. sata_x2 i 3.3v (filtered) sata crystal input
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 19 pin name type voltage functional description sata_is0#/gpio10 i/o 3.3v sata interlock switch port 0 (input) / gpio 10 ghi#/sata_is1#/gpi o6 i/o 3.3v ghi# output to cpu / sata inte rlock switch port 1 (input) / gpio 6 smartvolt/sata_i s2#/gpio4 i/o 3.3v reduce system voltages / sata interlock switch port 2 (input) / gpio 4 ssmuxsel/sata_is 3#/gpio0 i/o od 3.3v (5v tolerance) speedstep mux select (output) / sata interlock switch port 3 (input) / gpio0 note: for each port there is a pin (sata_is) for sensing th e status of the external interlock switch. if the motherboard implements sata interlock switches, it should c onnect the statuses of the sw itches to those pins. the sb600 will sense the statuses of those pins and can generate a pme or in terrupt when the states change. normally, an inter-lock switch is required for supporting hot plug. 3.7 power management / north bridge interface pin name type voltage functional description cpu_stp#/ dpslp_3v#* o 3.3v (5v tolerance) stop cpu clock [intel] / deep sleep (3.3v) cpu_stp#: stop cpu clock [intel ]. output to the external clock generator / nb to turn off the processor clock. it is used to support c3/c4 states and speedstep transitions. assertion takes place at an interval (programmed by an sb register) after stpgnt message has been received by the system. de-assertion causes the nb or external clock generator to turn on the processor, and that takes place (a) in a sleep state: after a wake-up event is triggered; (b) in a c3/c4/speedstep transition: at a certain time interval after its own assertion. dpslp_3v#: deep sleep (3.3v) [banias/dothan/yonah platforms only]. this signal behaves identically with the cpu_stp# signal, only that it goes to the cpu directly (see note below). dprslpvr o 3.3v deeper sleep voltage regulator: [intel] - assertion causes the voltage regulator to output the lower ?deeper sleep? core voltage to the cpu during c4 of s1-m states. assertion takes place sometime after cpu_stp# is asserted. de-assertion causes the volt age regulator to output the normal cpu core voltage for the cpu to exit the c4 state. de-assertion takes place sometime after de-assertion of cpu_stp# lpc_pme#/ gevent3# i/o s5_3.3v lpc pme# input / general event 3 lpc_smi#/ extevnt1# i/o 3.3v (5v tolerance) lpc smi# input / external event 1 pci_pme#/ gevent4# i/o s5_3.3v pci pme# input / general event 4 dpslp_od#*/gpio37 i/o 3.3v (5v tolerance) dpslp_od# / gpio 37 dpslp_od#: deep sleep (open drain) [p4 platforms only]. asserted by the sb600 to stop the processor?s clock. this signal behaves identically with the cpu_stp#/dpslp_3v# signal. this pin can also be used as gpio 37.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 20 pin name type voltage functional description pwr_btn# i s5_3.3v power button: the power button will cause an smi# or sci to indicate a system request to go to a sleep state. if the system is already in a sleep state, this signal will cause a wake event. if pwrbtn# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the s5 state with only the pwrbtn# available as a wake event. override will occur even if the system is in the s1 state. this signal has an internal pull-up resistor. pwr_good i s5_3.3v sb power good input assertion of pwr_good by the sb power good circuit on the motherboard indicates that power supplies to the sb are valid. assertion takes place so metime after nb power good is asserted. de-assertion of pwr_good by the sb power good circuit indicates that the power supplies to the sb are not valid. de-assertion takes place sometime after slp_s3# or slp_s5#?s assertion, or after power supply power good is de-asserted. ri#/extevnt0# i/o s5_3.3v ring indicator / external event 0 shutdown#/gpio5/ smartvolt2 i/o s0 system shutdown / gpio 5/smartvolt2 system shutdown: assertion will cause the sb600 to assert slp_s3# and slp_s5# to force system to transition to s5 immediately, without waiting for the stpgnt message from the processor. smartvolt2: used for smart power management slp_s3# o s5_3.3v s3 sleep power plane control assertion of slp_s3# shuts off power to non-critical components when system transitions to s3, s4, or s5 states. assertion takes place sometime after cpu_stp# is asserted. de-assertion of slp_s3# turns on power to non-critical components when system transitions from s3, s4, or s5 back to s0. de-assertion take s place sometime after a wake-up event has been triggered. slp_s5# o s5_3.3v s5 sleep power plane control - assertion of slp_s5# shuts power off to non-critical components when system transitions to s4 or s5 state. assertion takes place sometime after cpu_stp# is asserted. de-assertion of slp_s5# turns on power to non-critical components when transitioning from s4/s5 back to s0 state. de-assertion takes place sometime after a wake-up event is triggered. smbalert#/ thrmtrip#/ gevent2# i/o s5_3.3v smbus alert / thermal trip / general event 2 thermal trip: signal indicates to the sb600 that a thermal trip has occurred. its assertion will cause the sb600 to transition the system to s5 im mediately, without waiting for the stpgnt message from the processor.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 21 pin name type voltage functional description sus_stat# od s5_3.3v suspend status - assertion by the sb600 indicates that the system will be entering a low-power state soon. the signal is monitored by those devices with memory that needs to switch from normal refresh to suspend refresh mode when the system transitions to a low-power state. assertion takes place after the stop grant message from the cpu is received by the system. de-assertion by the sb600 indicates that the system is exiting a low power state now and is returning to s0. de- assertion timing for intel platforms is as follows: (a) i n s1: following a wake-up event, after slp# is de-asserted; (b) in s2/s3: following a wake-up event, at a programmable interval after cpu_stp# is de- asserted; (c) in s4/s5: after a wake -up event is triggered. de-assertion for amd platforms takes place after ldt_stp# is de - asserted. tempin3/ talert#/ gpio64 i/o 3.3v temperature monitor input 3/ thermal alert / gpio 64 thermal alert: the signal is a thermal alert to the sb600. sb600 can be programmed to generate an smi#, sci, or irq13 through gpe, or generat e an smi# without gpe in response to the signal?s assertion. see the sb600 register reference manual for details. s3_state/gevent5 # i/o s5_3.3v k8 s3 state [amd]: assertion of s3_state by the sb600 indicates to the power supply that the system has transitioned into s3 state. asserted after the sleep s3 command is completed. de-assertion indicates that the system is leaving s3 state. de-assertion takes place after sus_stat# is de-asserted. wake#/gevent8# i/o s5_3.3v pci express wake /general event 8 wake# signal is required fo r pci-e devices. the pci-e interface is off the nb, but t he acpi wake# is controlled by sb. this signal is routed from the pci-e device/slot to the sb. note: the wake# is in s5 domain so it is active when the system is in s5 state. care must be taken when plugging-in in the pci-e devices: the system should be transitioned in to g3 state (s5 power off) before a pci-e device is installed. plugging in a pci-e device when the system is in s5 state may cause the system to wake up. that is because the wake# si gnal driven by the pci-e device may transition momentarily to active state when the device is installed but has not been initialized to drive the signal in inactive state. ( note: hot plugging of pci-e devices is not supported in the pc architecture as, given the physical design of the interface, power will be interrupted during installation.) usb_oc9#/slp_s2/g pm9# i/o s5_3.3v usb over current 9 / s2 sleep control / gpm9 s2 sleep control: assertion of slp_s2 shuts off clocks when system transitions to s2 state, and it takes place sometime after cpu_ stp# is asserted. de-assertion of slp_s2 tu rns on clocks when system transition s from s2 back to s0, and it takes place sometime after a wake-up event has been triggered.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 22 pin name type voltage functional description slp#/ldt_stp# od [intel]/ o [amd] cpu_pwr sleep [intel] / ldt stop [amd] sleep (intel platforms only; not applicable to socket 775 platforms) - assertion of slp# causes the cpu to transition from stop grant state (c2) to sleep state (c3/c4). the signal is also used during speedstep transitions. assertion takes place at an interval (programmed by an sb register) after stpgnt message is received by the system. de-assertion of slp# causes cpu to return from sleep state (c3/c4) to stop grant stat e (c2). the signal is also used when bringing system from s1/s2/s3/s4/s5 back to s0. de-assertion takes place following a wake-up event: (a) in s1: at an interval (programmed by an sb register) after de-assertion of cpu_stp#; (b) in s2: after slp_ s2 is de-asserted; (c) in s3/s4/s5: after sl p_s3# is de-asserted; (d) in c3/c4, and during a speedstep transition: at an interval (programmed by an sb register) after de-assertion of cpu_stp#. ldt stop [amd] - assertion of ldtstop_l on the cpu causes it to enter c3, or s1/s2/s3/s4/s5. assert ion takes place: (a) for s1/s2/s3/s4/s5: after sus_stat # is asserted; (b) for c3: after the stpgnt message is received by the system. de-assertion of ldtstop_l causes the cpu to return to c0 or s0 state. de-assertion takes place following a wake- up event: (a) in s1: at an interval (programmed by an sb register) after de-assertion of cpu_stp#; (b) in s2: after slp_ s2 is de-asserted; (c) in s3/s4/s5: after sb pwr_good is asserted; (d) in c3: at an interval (programmed by an sb register) stpclk#/ allow_ldtstp i/ o cpu_pwr stop clock signal to cpu [intel] / allow ldt_stp# assertion [amd] stop clock signal to cpu [intel]: assertion of stpclk# causes the cpu to issue a stop grant acknowledge transaction and transition from the normal (c0) sate to the stop grant state (c2). the assert ion is initiated by software, during an acpi or speedstep tr ansition. de-assertion of stpclk# brings the cpu back to the normal (c0) sate. see section 4.2 for detailed de-assertion timing. allow ldt_stp# [amd]: it is an input from nb to allow assertion of ldt_stop#. when allow_ldtstp is de- asserted, sb600 cannot assert ldt_stop#. allow_ldtstp can be used to implement stutter mode operation for the cpu. * note: dpslp_3v# and dpslp_od# are the same signal, with the former being a push-pull and the latter an open drain signal. either one or both of them can be used to im plement the deep sleep function of the cpu. however, for output to a logic that does not have 3.3v input, using dp slp_od# will eliminate the need for a level shifter.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 23 3.8 processor interface pin name type voltage functional description a20m#/sid o cpu_pwr a20 mask [intel] / si data [amd], open-drain cpu_pg/ldt_pg o cpu_pwr power good to cpu [intel] / ldt power good [amd] cpu_pwr i cpu_pwr cpu i/o voltage ferr# i cpu_pwr floating point error pending at cpu [intel] ignne#/sic o cpu_pwr ignore numeric ex ception [intel] / si clock [amd], open- drain init# o cpu_pwr cpu initialization [intel] intr/lint0 o cpu_pwr intr pin [intel ] / interrupt signal to cpu?s lint0 ldt_rst#/dprstp#/ prochot# i/o cpu_pwr ldt reset# [amd] / cpu deeper stop# [intel yonah] / processor hot [intel non-yonah] ldt reset# (amd; 2.5v): reset signal to the cpu. assertion of ldt_rst# causes the cpu to transition into a low power state and to de-assert memclkea/b and assert memrest_l. assertion of ldt_rst# takes place sometime after sb pwrgood has been de-asserted. de-assertion of ldt_rst# allows memreset_l to be de- asserted and memclk to be enabled. de-assertion of ldt_rst# takes place so metime after sb pwr_good has been asserted. cpu deeper stop# [intel yonah]: inverted dprslpvr assertion takes place sometime after cpu_stp# is asserted. de-assertion takes place sometime after de-assertion of cpu_stp# processor hot [intel, non-yonah ) : similar to talert# nmi/lint1 o cpu_pwr nmi pin[intel] / n on maskable interrupt to cpu?s lint1 smi# o cpu_pwr system management interrupt to cpu [intel] 3.9 smbus interface / genera l purpose open collector pin name type voltage functional description scl0/gpoc0# * i/o 3.3v (5v tolerance) smbus clock 0 / general purpose open collector 0 sda0/gpoc1# * i/o 3.3v (5v tolerance) smbus data 0 / general purpose open collector 1 scl1/gpoc2# * i/o s5_3.3v (to support asf) smbus clock 1 / general purpose open collector 2 sda1/gpoc3# * i/o s5_3.3v (to support asf) smbus data 1 / general purpose open collector 3 smbalert#/ thrmtrip#/ gevent2# i/o s5_3.3v smbus alert# / thermal trip / general event 2 sm bus alert: this signal is used to wake the system or generate an smi#. if not used for smbalert#, it can be used for thermal trip or as a gevent. * note: sda1 and scl1 smbus interface is dedicated for asf devices only. it should not be used to connect to any other devices.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 24 3.10 real time clock interface pin name type voltage functional description rtc_gnd ? analog gnd rtc analog ground rtc_irq#/gpio69 i/o s5_3.3v/vbat rtc interrupt / gpio 69 rtcclk i/o s5_3.3v/vbat 32 khz input for exte rnal rtc / 32 khz output for internal rtc vbat i s5_3.3v/vbat rtc battery supply x1 i s5_3.3v/vbat rtc crystal oscillator input 1 (internal rtc) x2 o s5_3.3v/vbat rtc crystal oscillator input 2 (internal rtc) 3.11 reset / clocks / ate pin name type voltage functional description a_rst# o 3.3v (5v tolerance) pci host bus reset. asserted during transition to s3/s4/s5 to reset all devices in the sb6 00 or connected to it, except the acpi logic in the sb600 14m_osc i 3.3v 14.318 mhz clock rsmrst# i s5_3.3v resume reset from motherboard ? assertion of rsmrst# resets all sb600 registers to their default values. it also causes all reset signals originating from the sb600 (a_rst#, pcirst#, ldt_rst#, az_rst#, ac_rst#) to be issued. rsrmt# should be asserted when system power is being applied. type-i straps are captured on the rising edge of rsrmt# during its de- assertion. rsmrst# should be de-asserted sometime after s5 power is up, and should stay de-asserted until system power is removed. sys_reset#/gpm7# i/o s5_3.3v system reset / gpm 7 system reset: signal coming from the power button circuit signaling a reset for the system. on receiving the signal, the sb600 asserts all reset signals that originate from the sb600 including: a_rst#, pcirst#, ldt_rst#, az_rst#, and ac_rst#; it also resets all sb600 registers to their default values. test0 i s5_3.3v ate test 0 test1 i s5_3.3v ate test 1 test2 i s5_3.3v ate test 2 3.12 general purpose i/o the gpio pins of the sb600 are multiplexed with othe r functions. for information on how to configure the gpio pins for the desired functions, see the sb600 register reference manual (oem). the table below lists all the gpio pins on the sb600. the default type column shows the state of the pin (default function) after de-assertion of the pci host bus reset (a_rst#), which happens after power up or after system reset. signals that are in input state afte r reset will be tri-state (ts) if they do not have any internal pu (pull up ) or pd (pull do wn). for pins that have pu or pd in ternally, their states after reset will depend on the pu or pd: for signals with pu, the stat e will be high and for signals with pd the state will be low. the pu and pd shown are enabled by default after pci reset and can be disabled by system bios.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 25 pin name (default function* in blue ) type voltage power domain default type* functional description ssmuxsel / sata_is3#/gpio0 i/od 3.3v(5v tolerance) s0 output (low) speedstep tm (gv1 only) mux select / serial ata interlo ck switch port 3 / gpio 0 rom_cs#/ gpio1** i/o 3.3v(5v tolerance) s0 output (high) or input (pu), depending on strapping rom chip enable / gpio 1 spkr/ gpio2 i/o 3.3v(5v tolerance) s0 input (ts) speaker / gpio 2 fanout0/ gpio3 i/o 3.3v(5v tolerance) s0 input (pu) fan pwm output 0 / gpio 3 smartvolt/ sata_is2#/ gpio4 i/o 3.3v(5v tolerance) s0 input (ts) smartvoltage select / serial ata interlock switch port 2 / gpio 4 shutdown#/ gpio5 /s martvolt2 i/o 3.3v(5v tolerance) s0 input (ts) system shutdown / gpio 5/smartvolt2 ghi# /sata_is1#/gpio 6 i/od 3.3v(5v tolerance) s0 output (ts) ghi# output to cpu (gv1 only)/ serial ata interlock switch port 1 / gpio 6 wd_pwrgd/ gpio7*** i/o 3.3v(5v tolerance) s0 output (high) or input (ts), depending on strapping watchdog power good for nb / gpio 7 ddc1_sda/ gpio8 i/o 3.3v(5v tolerance) s0 input (ts) ddc1 serial data / gpio 8 ddc1_scl/ gpio9 i/o 3.3v(5v tolerance) s0 input (ts) ddc1 serial control / gpio 9 sata_is0# /gpio10 i/o 3.3v(5v tolerance) s0 input (ts) serial ata interlo ck switch port 0 / gpio 10 spi_do/ gpio11 i/o s5_3.3v s5 input (pd) spi rom data out / gpio 11 spi_di/ gpio12 i/o s5_3.3v s5 input (pd) spi rom data in / gpio 12 lan_rst# /gpio13 o 3.3v(5v tolerance) s0 output (low) lan reset / gpio 13 rom_rst# /gpio14 ? i/o 3.3v(5v tolerance) s0 output (low) rom reset ? / gpio 14 ide_d[15:0] /gpio[30:1 5] i/o 3.3v(5v tolerance) s0 output (high) ide dat a [15:0] / gpio [30:15] spi_hold#/ gpio31 i/o s5_3.3v s5 input (pu) spi rom hold / gpio 31 spi_cs#/ gpio32 i/o s5_3.3v s5 input (pu) spi rom chip select / gpio 32 inte# /gpio33 i/o 3.3v(5v tolerance) s0 input (pu) pci interrupt e / gpio 33 intf# /gpio34 i/o 3.3v(5v tolerance) s0 input (pu) pci interrupt f / gpio 34 intg# /gpio35 i/o 3.3v(5v tolerance) s0 input (pu) pci interrupt g / gpio 35 inth#/ gpio36 i/o 3.3v(5v tolerance) s0 input (pu) pci interrupt h / gpio 36 dpslp_od# /gpio37 i/o 3.3v(5v tolerance) s0 output (ts) deep sleep (open drain) / gpio 37 ac_bitclk /gpio38 i/o 3.3v(5v tolerance) s0 input (pd) ac ?97 bit clock / gpio 38 ac_sdout /gpio39 i/o 3.3v(5v tolerance) s0 output (low) ac ?97 se rial data out / gpio 39 ac_sync /gpio40 i/o 3.3v(5v tolerance) s0 output (low) ac ?97 sync / gpio 40
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 26 pin name (default function* in blue ) type voltage power domain default type* functional description spdif_out / pciclk7/gpio41 i/o 3.3v(5v tolerance) s0 output (low) spdif serial output / 33mhz pci clock 7 / gpio41 acz_sdin[2:0] / gpio[44:42] i/o s5_3.3v s5 input (pd) ac ?97 or hd audio se rial data in [2:0] / gpio[44:42] ac_rst# /gpio45 i/o s5_3.3v s5 output (low) ac ?97 reset# / gpio45 az_sdin3/ gpio46 i/o s5_3.3v s5 input (pd) hd audio serial data in 3 / gpio46 spi_clk /gpio47 i/o s5_3.3v s5 input (pd) spi rom clock / gpio 47 fanout[2:1]/ gpio[49: 48] i/o 3.3v s0 input (pu) fan pwm output [2:1] / gpio [49:48] fanin[2:0]/ gpio[52:50] i/o 3.3v s0 input (ts) fan tachometer input [2:0] / gpio [52:50] vin[7:0]/ gpio[60:53] i/o 3.3v s0 input (ts) voltag e input [7:0] / gpio [60:53] tempin[2:0]/ gpio[63:6 1] i/o 3.3v s0 input (ts) temperature monitor input [2:0] / gpio [63:61] tempin3/talert#/ gpio64 i/o 3.3v s0 input (ts) temperature monitor input 3 / temperature alert / gpio64 bmreq#/req5#/ gpio65 i/o 3.3v s0 input (ts) bus master request / pci request 5 (output) / gpio 65 llb#/ gpio66 i/o s5_3.3v s5 input (pu) low-low battery / gpio 66 sata_act# /gpio67 od 3.3v s0 output (ts) serial ata activity / gpio 67 ldrq1#/gnt5#/ gpio68 i/o 3.3v(5v tolerance) s0 input (pu) lpc dma req 1 / pci grant 5 / gpio 68 rtc_irq# / gpio69? i/o s5_3.3v/v bat s5 input (pu) rtc interrupt / gpio 69 req[4:3]# /gpio[71:70] i/o 3.3v(5v tolerance) s0 input (pu) pci request [4:3] (input) / gpio [71:70] gnt[4:3]# /gpio[73:72] i/o 3.3v(5v tolerance) s0 output (ts) pci grant [4:3] / gpio [73:72] notes: * the ?default function? and the ?default type? refer to function and type of the pin after de-assertion of pci host bus reset (a_rst#), i.e., right after system power up or reset. ** rom_cs# is the default function when the sb600 is strapped to use a pci rom ( pci rom is not supported for asic revision a21 and onwards ). *** the function of wd_pwrgd (watchdog power good) has not been qualified. this ball should only be used as gpio7. ? pci rom is not supported for asic revision a21 and onward s, for which the default fu nction of the pin is thus gpio14. the gpio68 and gnt5# functions are not present in asi c versions a11-a13. in those versions, the default function is therefore lpc dma req 1#. ? rtc_irq# is the default function when t he sb600 is strapped for external rtc mode. 3.13 external event / general event / general power management / general purpose open collector the extevent/gevent/gpm/gpoc pins of the sb600 are multiplexed with other functions. for information on how to configure the extevent/geven t/gpm/ gpoc pins for the desired functions, see the sb600 register reference manual (oem). the table below lists all the extevent/gevent/gp m/gpoc pins on the sb600. the default type column shows the state of the pi n (default function) after de-assertion of the pci host bus reset (a_rst#), which happens after power up or after syst em reset. signals that are in input state after reset
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 27 will be tri-state (ts) if they do not have any internal pu (pull up ) or pd (pull down). for pins that have pu or pd internally, their states after reset will depend on the pu or pd : for signals with pu, the state will be high and for signals with pd the state will be low. the pu and pd shown are enabled by default after pci reset and can be disabled by system bios. pin name (default function in blue ) type voltage power domain default type functional description ri#/ extevent0# i/o s5_3.3v s5 input (pu) ring indicator / external event 0 lpc_smi#/ extevent1# i/o 3.3v(5v tolerance) s0 input (pu) lpc smi / external event 1 smbalert#/ thrmtr ip# /gevent2# i/o s5_3.3v s5 input (pu) sm bus alert / thermal trip / general event 2 lpc_pme#/ gevent3# i/o s5_3.3v s5 input (pu) lpc pme (input) / general event 3 pci_pme#/ gevent4# i/o s5_3.3v s5 input (pu) pci pme (input) / general event 4 s3_state/ gevent5# * i/o s5_3.3v s5 output (low) or input (pu), depending on strapping amd s3 state / general event 5 see note 1 below. usb_oc[7:6]#/ gevent[7:6]# i/o s5_3.3v s5 input (pu) usb over current [7:6] / general event [7:6] wake#/ gevent8# i/o s5_3.3v s5 input (pu) pci express wake / general event 8 usb_oc[4:0]#/ gpm[4: 0]# i/o s5_3.3v s5 input (pu) usb ov er current [4:0] / gpm [4:0] usb_oc5#/ddr3_rs t#/ gpm5# i/o/ od s5_3.3v s5 output (low) usb over current 5 / ddr3 memory reset / gpm 5 blink/ gpm6# i/o s5_3.3v s5 input (pu) led blink / gpm 6 sys_reset#/ gpm7# i/o s5_3.3v s5 input (pu) system reset / gpm 7 usb_oc8#/ az_dock_rst#/ gpm8# i/o s5_3.3v s5 input (pu) usb over current 8 / hd audio dock reset / gpm 8 usb_oc9#/slp_s2/ gpm9# i/o s5_3.3v s5 input (pd) usb over current 9 / sleep s2 indicator / gpm 9 scl0/ gpoc0# i/o 3.3v(5v tolerance) s0 input (ts) smbus clock 0 / general purpose open collector 0 sda0/ gpoc1# i/o 3.3v(5v tolerance) s0 input (ts) smbus data 0 / general purpose open collector 1 scl1/ gpoc2# ** i/o s5_3.3v (to support asf) s5 input (ts) smbus clock 1 (asf) / general purpose open collector 2 see note 2 below. sda1/ gpoc3# ** i/o s5_3.3v (to support asf) s5 input (ts) smbus data 1 (asf) / general purpose open collector 3 see note 2 below. * note 1: s3_state is the default function when the sb600 is strapped for amd cpu mode . if strapped for intel cpu mode(gevent5#), default is input (pu) for sb600 a1 1-a13 and input (ts) for sb600 a21 and onwards. ** note 2: sda1 and scl1 smbus interface is dedicated for asf devices only. it should not be used to connect to any other devices.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 28 3.14 ac ?97 link interface pin name type voltage functional description ac_bitclk/gpio38 i 3.3v (5v tolerance) ac ?97 interface bit clock / gpio 38 ac_rst#/gpio45 od/ i s5_3.3v ac ?97 interface reset (od) / gpio45 acz_sdin[2:0]/gpio[44:42] i/o s5_3.3v ac ?97/hd audio serial data input from codec [2:0] / gpio [44:42] ac_sdout /gpio39 i/o 3.3v (5v tolerance) ac ?97 serial data out put to codec / gpio 39 ac_sync /gpio40 i/o 3.3v (5v tolerance) ac ?97 sync signal to codec / gpio40 spdif_out /pciclk7/gpio41 i/o 3.3v (5v tolerance) spdif serial output / 33mhz pci clock 7 / gpio41 3.15 hd audio interface pin name type voltage functional description az_bitclk o 3.3v hd audio interface bit clock az_rst# o s5_3.3v hd audio interface reset acz_sdin[2:0]/gpio[44:42] i/o s5_3.3v ac ?97/hd audio serial data input from codec [2:0] / gpio [44:42] az_sdin3/gpio46 i/o s5_3.3v hd audio serial data input from codec 3/ gpio 46 az_sdout o 3.3v hd audio serial data output to codec az_sync o 3.3v hd audio sync signal to codec 3.16 xbus rom access interface note: xbus rom is not supported for asic revision a21 and onwards. pin name type voltage functional description ad[15:0]/roma[18:11, 9:2] i/o 3.3v (5v tolerance) pci bus address/data [15:0] / rom address [18:11, 9:2] ad[23:16]/romd[7:0] i/o 3.3v (5v tolerance) pci bus address/data [ 23:16] / rom data [7:0] cbe0#/roma10 i/o 3.3v (5v tolerance) command/byte enable[0] / rom address [10] cbe1#/roma1 i/o 3.3v (5v tolerance) command/byte enable[1] / rom address [1] cbe2#/romwe# i/o 3.3v (5v tolerance) command/byte enable[2] / rom we # devsel#/roma0 i/o 3.3v (5v tolerance) device select / rom address [0] par/roma19 i/o 3.3v (5v tolerance) pci bus par/rom address[19] rom_cs# / gpio1 i/o 3.3v (5v tolerance) rom chip enable; gpio1
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 29 3.17 spi rom interface spi rom is supported up to 33 mhz. the burst read and fast read cycles are not supported. pin name type voltage functional description spi_di/gpio12 i/o s5_3.3v spi data in / gpio 12 spi_do/gpio11 i/o s5_3.3v spi data output / gpio 11 spi_clk/gpio47 i/o s5_3.3v spi clock / gpio 47 spi_hold#/gpio31 i/o s5_3.3v spi hold# / gpio 31 spi_cs#/gpio32 i/o s5_3.3v spi chip select# / gpio 32 3.18 hardware monitor pin name type voltage functional description fano0/gpio3 i/o 3.3v (5v tolerance) fan pwm output 0 / gpio 3 fano1/gpio48 i/o 3.3v (5v tolerance) fan pwm output 1 / gpio 48 fano2/gpio49 i/o 3.3v (5v tolerance) fan pwm output 2 / gpio 49 fanin0/gpio50 i/o 3.3v (5v tolerance) fan tachometer input 0 / gpio 50 fanin1/gpio51 i/o 3.3v(5v tolerance) fan tachometer input 1 / gpio 51 fanin2/gpio52 i/o 3.3v(5v tolerance) fan tachometer input 2 / gpio 52 temp_comm i (analog gnd ) temperature sensor diode current return path. tempin0/gpio61 i/o 3.3v temperature monitor input 0 / gpio 61 tempin1/gpio62 i/o 3.3v temperature monitor input 1 / gpio 62 tempin2/gpio63 i/o 3.3v temperature monitor input 2 / gpio 63 tempin3/talert#/gpio64 i/o 3.3v temperature monitor input 3 / temperature has reached cautionary state / gpio 64 vin0/gpio53 i/o 3.3v voltage monitor input 0 / gpio 53 vin1/gpio54 i/o 3.3v voltage monitor input 1 / gpio 54 vin2/gpio55 i/o 3.3v voltage monitor input 2 / gpio 55 vin3/gpio56 i/o 3.3v voltage monitor input 3 / gpio 56 vin4/gpio57 i/o 3.3v voltage monitor input 4 / gpio 57 vin5/gpio58 i/o 3.3v voltage monitor input 5 / gpio 58 vin6/gpio59 i/o 3.3v voltage monitor input 6 / gpio 59 vin7/gpio60 i/o 3.3v voltage monitor input 7 / gpio 60 avdd - 3.3v (analog power) hardware monitor analog pwr avss - analog ground hardwa re monitor analog gnd
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 30 3.19 power and ground signal name voltage/ ground acpi state gnd reference note description vdd_[12:1] 1.2v s0-s2 vss - core power vddq_[28:1] 3.3v s0-s2 vss - 3.3v i/o power s5_1.2v_[4:1] 1.2v s0-s5 vss 1.2v s5 power s5_3.3v_[6:1] s5_3.3v s0-s5 vss - 3.3v s5 power avddck_3.3v 3.3v s0-s2 avssck 1 3.3v power for analog plls avddck_1.2v 1.2v s0-s2 avssck 1.2v power for analog plls pcie_pvdd 1.2v s0-s2 pcie_vss 1 a-link express ii pll power pcie_vddr[13:1] 1.2v s0-s2 pcie_vss 1 a-link express ii analog power avdd_sata[15:1] 1.2v s0-s2 avss_sata 1 sata analog power pllvdd_sata_[2:1] 1.2v s0-s2 avss_sata 1 sata pll power xtlvdd_sata 3.3v s0-s2 avss_sata 1 sata xtal power vbat 2.5 - 3.6v bat - rtc_gnd - rtc backup power avddc s5_3.3v s0-s5 / s0-s3 avssc 1, 2 analog power for usb phy pll avddrx[4:0] s5_3.3v s0-s5 / s0-s3 avss_usb 1, 2 analog power for usb phy rx avddtx[4:0] s5_3.3v s0-s5 / s0-s3 avss_usb 1, 2 analog power for usb phy tx usb_phy_1.2v[5:1] 1.2v s0-s5 / s0-s3 avss_usb 2 1.2v usb phy standby power v5_vref 5v s0-s2 vss - 5v reference voltage for pci interface cpu_pwr cpu i/o voltage s0-s2 vss 3 cpu i/o reference voltage vss_[57:1] gnd - - - digital ground avssck gnd - - - common ground for analog plls pcie_pvss gnd - - - a-link express ii pll ground pcie_vss[42:1] gnd - - - a-link express ii analog ground avss_sata[27:1] gnd - - - sata analog ground (plane) rtc_gnd analog gnd - - - rtc analog ground avssc gnd - - - analog ground for usb phy pll. avss_usb_[33:1] gnd_usb - - - analog ground for usb phy note 1: these power rails should be filtered. note 2: these power rails can be tied to s0-s5 or s0-s3 power. note 3: cpu_pwr is 2.5v/1.8v for amd platforms , and is cpu_pwr for intel platforms.
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 31 3.20 pin straps straps are captured on the rising edge of rsmrst# and pwr_good. there are two kinds of straps: type i and type ii. type i straps become valid immediat ely after capture on the rising edge of rsmrst#. this type of strap is used by modules in the s5 power well and is therefore captured only once, when power is first applied to the chip. all other straps (type ii) become valid after pwr_good is asserted in order to prevent the strap logic that resides in t he standby power well from being driven by un-powered logic. type ii straps are captured every time the system s powers up from the s5 state. transition from s3 to s0 does not trigger capture. s5_1.2v straps (board) pwrgood setup time for capture 0 parameter min max hold time for capture 1310.5 rsmrst# vdd t ts th ns unit ns ts th straps type i straps i capture straps type ii straps i straps type i straps type ii undefined straps ii capture straps ii don't care figure 3-1: straps capture straps are classified into two groups: standard an d debug. standard straps are required for selecting different chip options at power-up. debug straps are used for debugging purposes only. debug straps are not required to be populated for production boards. however, there should be provisions for connecting pus or pds on the debug strap signals if they are not used for normal system operation. the description column in table 3-1 and table 3-2 shows the function of every strap signal in the design. all straps are defined such that in the most likel y scenario of operation, they will be set to the recommended (or safest) values. the values shown in the description column are the external board strap values, with 3.3v being a pull-up and 0v a pull-down. table 3-1: standard straps pad name strap name type description ac_sdout / gpio39 defaultmode ii enable/disable additional straps for debugging (see table 3-2 ) 0v ? use hardcoded defaults for debug straps ( default ) 3.3v ? enable additional debug straps
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 32 pad name strap name type description { pciclk1, pciclk0 } { romtype_1, romtype_0 } ii romtype_1 romtype_0 rom type 3.3v 0v lpc rom ( default ) (supports both lpc and pmc rom types) 3.3v 3.3v pci (x bus) rom (not supported for asic revision a21 and onwards.) 0v 0v firmware hub 0v 3.3v spi rom pciclk6 cpu_type ii defines the type of cpu 0v ? intel processors ( default for intel platform) 3.3v ? amd k8 processors (default for amd platform pciclk4 selusbpll48 ii select 48mhz usb clock or internal pll 0v ? use external 48mhz clock (default) 3.3v ? use internal pll48 table 3-2: debug straps pad name strap name type description ad [28] shortreset ii generate a short reset 0v ? use short reset (reserved, do not use) 3.3v ? use long reset ( default ) (internal pu of 15k ? ) ad [27] pcipllbyp ii bypass pci pll 0v ? bypass internal pll clock . use req3# as a-link bypass clock use gnt3# as b-link bypass clock 3.3v ? use internal pll-generated pll clk ( default ) (internal pu of 15k ? ) ad[26] acpibclkbyp ii bypass acpi_bclk 0v ? bypass internal generated acpi_bclk. gnt0# as acpi_bclk bypass clock. 3.3 v ? use internal generated acpi_bclk ( default ) (internal pu of 15k ? ) ad[25] ideclkbyp ii bypass ide clk 0 v ? bypass internal ide clk use gnt2# as ide 66mhz bypass clock. use req2# as ide 50mhz bypass clock. use req1# as ide 33mhz bypass clock. 3.3 v ? use internal pll ide clk ( default ) (internal pu of 15k ? ). ad[24] i2cromen ii a-link express-ii core strap from i2c rom enable 0v ? getting the value from i2c eprom. i2c eprom address set to all zeroes. use gnt4# as sda use req4# as scl. 3.3 v ? use default value ( default ) (internal pu of 15k ? )
?2007- 2008 advanced micro devices, inc. signal description sb600 databook proprietary page 33 pad name strap name type description ad[23] bootfailtimeren ii bootfail timer enable 0v ? enable bootfail timer 3.3v ? use default value (bootfail timer off ) ( default ) (internal pu resistor -15k ? ) table 3-3: additional straps the following strap is not captured by the straps l ogic, but is required to set the correct rtc mode. pad name strap name description rtcclk ? if a clock is applied to this pin and x1 is terminated, the chip will be set to external rtc mode. if this pin is pulled-up to s5_3.3v and a crystal is put on x1/x2, the chip will be set to internal rtc ( default )
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 34 4 power planes and pin states 4.1 power up and down sequences simple diagrams of the sb600 power up sequences for both the intel and amd platforms are shown in figure 4-1 through figure 4-4 below. a power detection circuit is int egrated into the sb600. this circuit will monitor sb pwrgd and will assert a_rst# (and ldt_rst# too on k8 -based platforms) for as long as sb pwrgd is false. after sb pwrgd has been asserted, a_rst# (followed by ldt_rst# on k8- based platforms), will be de-asserted. note that init# (to the cpu) is not asserted dur ing the power up sequence table 4-1 shows the timing requirements referenced in figure 4-1 through figure 4-4 . besides the illustrated requirements, it is also required t hat the ramp time for any rail be less than 40ms. table 4-1: sb600 power up/down sequence timing symbol min. max. description t1 note 1 3.3v(s5) to 1.2v(s5) t2 10 ms ? s5 power to resume reset (rsm_rst#) t2a ? 50 ms resume reset (rsm_rst#) ri se time (10% to 90%). sb600 has a schmitt trigger input with debouncing logic on this pin, so the value is relaxed relative to earlier ati sb designs. t3 31 ms ? rsmrst# de-asserted to start of rtc clock out from pin d3 on sb600. t6 note 15 vrm_pg to nb_pwrgd / core_pwrgd to nb_pwrgd t7 -22 ms 500 ms nb power good to sb_pwrgd. sb_pwrgd should be qualified by 3.3v(s0), +1.2v(s0) at 90%, and power supply pwrok. the nb and sb are targeted to use the same power good signal. the time difference between power good and system reset?s de-assertion is ~ 72ms. the nb requires 50ms, and that leaves ~22ms for the minimum lag between the nb and sb power goods. the 500ms maximum is an arbitrary number. t7a ? 50 ms sb_pwrgd rise time (10% to 90 %). see note 3 . sb600 has a schmitt trigger with de-bouncing logic on this pin, so the value is relaxed relative to earlier ati sb designs. t7b ? 1 ms sb_pwrgd fall time. t8 47 ms 66 ms sb_pwrgd to cpu_pg. cpu_pwrgd is driven by sb600 0 ns t8a note 4 100 ns a_rst# (pci host bus reset) to pcirst# t8b ? note 5 kb_rst# to a_rst# t8c 1.9 ms 2.1 ms pcirst# to ldt_rst# (amd only) see note 14. t8d 47 ms 66 ms sb_pwrgd to ldt_pg(amd only) t9 71 ms 73 ms sb_pwrgd to pci_rst# t9a 71ms 73 ms sb_pwrgd to a_rst# (t9-t8a) t10 -31 ms ? pcie_clkp/n stable to sb_pwrgd asserted. t11 36 ms 41 ms sb_pwrgd to stable pci clock 33 mhz. see note 9 . t12 1 ms ? pcirst# to cpu_rst# (cpu_rst# is driven by nb ) ? 15ns wake event (except pwrbutton) to slp_s3# / slp_s5# t13 note 16 200 ns ? wake event (pwrbutton) to slp_s3# / slp_s5#
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 35 symbol min. max. description t13a 80 ns ? sb_pwrgd must be de-asserted before vdd(ps pwok) drops more than 5% off the nominal value. note 10 t14 1 ns ? sb_pwrgd de-assertion to re sume reset (rsm_rst#) assertion. see note 11 . t15 5s ? [not illustrated] vbat to vdd 3.3 and 1.2 (s5 power). must be greater than 5 seconds to allow start time for the internal rtc. t16 31 ms sb_pwrgd to cpu_stp# de-assertion t17 31 ms sb_pwrgd to dprstp# de-assertion see notes 1-16 in the power up/down sequence timing notes section following the power up/down sequence diagrams.
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 36 t1 t2a s5 s5 g3 g3 s0 s5 straps vbat rtc clock in s5 3.3 s5 1.2 rsm_rst# a_rst# kb_rst# t8b pci_rst# t10 pcie clk t2 pci clk cpu_rst# (see note 1) (see note 5) t11 t8a t12 t9 cpu_stp# undefined(note 7) slp#/stop_clk# hi - z slp_s3#/ slp_s5# s0 power rails sb_pwrgd s0 straps vrm_pwrgd nb_pwrgd t6 t7 t7a cpu_pwrgd wake event pcie_wake_up# pwr_btn# ps pwok t13a t7b (see note 1 & 2) (see note 6) rtc clock out t3 dprstp# (see note 12) (see note 13) t16 t17 figure 4-1: sb600 power up/down sequence for platforms with intel processors
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 37 s3 s3 s0 vbat rtc clock a_rst# kb_rst# t8b pci_rst# t10 pcie clk pci clk cpu_rst# (see note 5) t11 t8a t12 t9 undefined(note 7) slp#/stop_clk# hi - z s0 power rails sb_pwrgd vrm_pwrgd nb_pwrgd t6 t7 t7a cpu_pwrgd wake event ps pwok t13a t7b (see note 1 & 2) slp_s3# pcie_wake_up# pwr_btn# slp_s5# gnd s5 3.3 s5 1.2 gnd gnd rsm_rst# gnd dprstp# (see note 12) (see note 13) t16 t17 cpu_stp# figure 4-2: sb600 s3/s0 power up/down sequence for platforms intel processors
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 38 figure 4-3: sb600 power up/down sequence for platforms with amd processors
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 39 figure 4-4: sb600 s3/s0 power up/down sequence for platforms with amd processors
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 40 power up/down sequence timing notes note 1: there are no specific power sequencing requirement s other than those indicated in note 2 below (and potentially also in pa_sb600ah1, depending on the asic revision that is used). the sb600 power rails are grouped in four different voltages: i. +5v, which includes v5_vref ii. +3.3v, which includes vddq iii. +1.2v, which includes vdd, avddck_1.2v, avdd_sata, pllvdd_sata pcie_pvdd, pcie_vddr iv. cpu_pwr (voltage is cpu-dependent) note 2: a. v5_vref is used in the sb600 for the 5v pci signa l tolerance. vddq (+3.3v) must not exceed v5_vref by more than 0.6v at any time during ra mp up, steady state, or ramp down. the suggested circuit below should be used to maintain relationship between v5_vref and vddq. +5v +3.3v ixp 5v vref vddq schottky diode recomended d1 1k 1uf figure 4-5: circuit for maintaining proper relationship between +v5_vref and vddq b. pcie_pvdd must ramp between 3s and 5ms later than vdd (core power) measured at 0.9v of each ramp as show below. see pa_sb600at for a detailed description of this requirement. figure 4-6: pcie_pvdd vs. vdd ramp requirement note 3: the sb600 will latch the straps after rising e dge of sb pwrgd only once. with debouncing of sb pwrgd, the latching of strap will occur at approx imately ~10ms after the rising edge of sb pwrgd. note 4 : typical time between a_rst# and pcirst# is 75ns. the measurement should be done at 10% of both signals. loading on the motherboard may caus e the measurement at 90% be more than the what is specified. note 5 : the kb_rst# should be de-asserted before a_rst# (ldt_rst#) is de-asserted. note 6: type ii standard and debug straps will be latch ed after sb pwrgd is asserted. the straps will be latched in the window of tsc(min) = 10ms to tsc(max) = 10ms + 1050ns after sb pwrgd. type i straps are latched on resume reset rising edge. see figure below.
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 41 figure 4-7: timing for latching of straps note 7 : slp# and stop_clk# are tri-stated by the sb6 00 on power up. the voltages on these signals will depend on the external pull up supply. note 8 : the sb600 will not monitor the allow_ldtstp signal on power up. this signal is only used on c3 transitions. note 9: the pci clock may be stable before t11 min. under some conditions; however in all cases, the pci clock is guaranteed to be stable only between t11 min. and max. note 10: the sb600 will monitor internally the power down event and protect the internal circuit during power down. this includes power down during the s3, s4, and s5 states. during an unexpected power failure or g3 state, the relationship between the 1.2v (vdd) and sb power good should be maintained to protect the sb600?s internal logic. note 11: the following figure shows the timing of sb pwrgd de-asserted to rsm_rst# de-asserted during a power down sequence. however, this timing on ly applies to s0 to g3 state transition, because g3 state is when both signals are inactivated. figure 4-8: timing for sb pwrgd de-asserted to rsm_rst# de-asserted note 12: dprstp# is asserted (low) until 32 ms after sb pwrgd is asserted. the signal may not be fully asserted to zero volt but may be seen at 300 mv max. this will still be considered a logic low by external logic. the dprstp# will be asserted only afte r the sb600 identifies the platform (which is done by reading the straps when sb pwrgd is a sserted). see the following graph for details.
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 42 figure 4-9: dprstp# fully de-asserted when sb pwrgd asserted note 13: since the sb does not drive the signal until 32 ms after sb pwrgd, on some power up cycles, cpu _ stp# may be asserted (low) until 32 ms after sb pwrgd is asserted. see the following figure for details. figure 4-10: cpu_stp# de-asserted when sb pwrgd asserted note 14: there is an approximately 200 ns max. glitch on ldt_rst# (label c in figure below), after the sb pwrgd is asserted. this glitch is c aused by the logic not driving the signal for this period of time, as this multifunctional pin is being configured to support either an amd or an intel cpu. this glitch happens right after sb pwrgd assertion, because this is the time when the sb straps are latched. the control signal will be in the process of being configured to ei ther ldt_rst# (amd platform) or dp rstp#//prochot (intel platform). prior to the sb_pwrgd assertion the ldt_rst# may be de-as serted as the internal logic is not initialized. the duration will depend on when the 3.3v or 1.2v rail ramps up. the de-assertion will be from the time when the 3.3.v or 1.2v rail ramps to 2.0v or 0.9 v respecti vely, to the time when sb_ pwrgd ramps up to 2.0v. due to the following two timing features regarding t he ldt_pg and ldt_rst#, the glitch on ldt_rst# should have no impact on the normal operation. 1. ldt_pg (cpu power good) is not asserted during t he glitch and thereafter for at least 42 ms; see label a in the figure below. 2. ldt_rst# is also asserted again, after this glitch , for at least 74 ms (label b in the figure below), which will ensure that the cpu will be reset properly befo re actual de-assertion of ldt_rst# takes place.
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 43 figure 4-11: glitch on ldt_rst# note 15: nb_pwrgd prerequisite timing is referred to in the power sequence section of the respective northbridge motherboard design guides. note 16: t13 is the duration between the time a wake event is seen by the sb600 and the de-assertion of the slp_s3# and slp_s5# signals. the timing shown here is based on a minimum loading of 50 pf for both the slp signals and the wake event signals. if the system board has additional loading, the time measured will be longer due to the slow rise time of the sign al. in this case the measurement is done at 90% of the fall time on wake event signal and 10% of the rise time of the slp signal rise time for a more accura te reading. see figure below. figure 4-12: t13 measurement points
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 44 4.2 acpi timing [tba]
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 45 4.3 pull-up/-down requiremen ts and integrated resistors table 4-2: external resistor requirements and integrated pull up/down interface signal name value for integrated / external resistor resistor type register for programming the integrated pu/pd ide_drq integrated 5.6k pull-down ? ide_iordy integrated 4.7k pull-up ? ide_irq integrated 10k pull-down ? ide_d7/gpio22 integrated 10k + integrated 27 ? see note (see gpio section below) ide_d[15:0]/gpio[30:15] integrated 27 ? series ide_a[2:0] integrated 27 ? series ? ide_cs[3,1]# integrated 27 ? series ? ide ide_dack#, iow#, ior#, integrated 27 ? series ?? pcie_calrp external 562 ? ( 1% tolerance ) reference resistor for the tx termination. pull-down to vss_pcie pcie pcie_calrn external 2.05k ( 1% tolerance ) reference resistor for the rx termination pull-up to vdd_pcie ? usb hsdm [ 9:0 ] - inte g rated 15k pull-down ? usb usb_hsdp[9:0]+ integrated 15k pull-down ? ac_bitclk/gpio38 integrated 10k pull-down (see gpio section below) acz_sdin[2:0]/ gpio[44:42] integrated 50k pull-down (see gpio section below) az_sdin3/gpio46 integrated 50k pull-down (see gpio section below) ac ?97 /hd audio ac_sdout/gpio39 integrated 10k pull-down (see gpio section below) a20m#/sid amd platforms: external 300 ? pu required. the pu should be tied to the same power used by the cpu i/o. intel platforms: pu not required, as i/o is push- pull pull-up [amd] ? processor cpu_pg/ldt_pg amd platforms: external 20k pd intel platforms: pd not required, as i/o is push- pull pull-down [amd] ?
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 46 interface signal name value for integrated / external resistor resistor type register for programming the integrated pu/pd ferr# amd platforms: pin unused. leave unconnected. intel platforms: external pull-up is required pull-up ? ignne#/sic amd platforms: external 300 ? pu required. pull up should be tied to the same power used by the cpu i/o. intel platforms: external pu not required, as i/o is push-pull pull-up [amd] ? init# pu not required, i/o is push-pull ? ? intr/lint0 pu not required, i/o is push-pull ? ? nmi/lint1 pu not required, i/o is push-pull ? ? smi# pu not required, i/o is push-pull ? ? stpclk#/allow_ldtst p amd platforms: external pu to cpu pwr intel platforms: pu not required, i/o is push-pull pull-up [amd] ? slp#/ldt_stp# amd platforms: external 20k pd intel platforms: not required if paired with rs600?s slp# pin; otherwise, it requires an external pu to cpu_pwr. pull-up / pull-down ? dprslpvr pu not required, i/o is push-pull (integrated pd when tri-stated) pull-down [integrated, when tri- stated] ? processor ldt_rst#/dprstp#/ prochot# amd platforms: external 20k pd intel platforms: not required if it is configured as dprstp# (i/o is push-pull). for prochot#, it requires external pu pull-down [amd] / pull-up [intel] ? pcirst# external 8.2k pull-down is required pull-down ? inte#/gpio33 integrated 8.2k pull-up (see gpio section below) intf#/gpio34 integrated 8.2k pull-up (see gpio section below) pci intg#/gpio35 integrated 8.2k pull-up (see gpio section below)
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 47 interface signal name value for integrated / external resistor resistor type register for programming the integrated pu/pd inth#/gpio36 integrated 8.2k pull-up (see gpio section below) ad[31:23] integrated 15k pull-up pm_reg 41h / pm_reg 40h default: pu enabled frame# integrated 8.2k pull-up ? trdy#/romoe# integrated 8.2k pull-up ? irdy# integrated 8.2k pull-up ? devsel#/roma0 integrated 8.2k pull-up ? stop# integrated 8.2k pull-up ? serr # integrated 8.2k pull-up ? pci_perr# integrated 8.2k pull-up ? lock# integrated 8.2k pull-up ? clkrun# integrated 8.2k pull-up ? req0# integrated 15k pull-up ? req1# integrated 15k pull-up ? req2# integrated 15k pull-up ? req3#/gpio70 integrated 15k pull-up (see gpio section below) req4#/gpio71 integrated 15k pull-up (see gpio section below) bmreq#/req5#/gpio65 external pu if used as req5# pull-up (see gpio section below) lad[3:0] integrated 15k pull-up ? ldrq0# integrated 15k pull-up ? ldrq1#/gnt5#/gpio68 integrated 15k pull-up (see gpio section below) lpc_smi#/extevnt1# integrated 8.2k pull-up (see gevent section below) serirq integrated 8.2k pull-up ? ga20in integrated 8.2k pull-up ? kbrst# integrated 8.2k pull-up ? spi_clk/gpio47 integrated 10k pull-down (see gpio section below) spi_di/gpio12 integrated 10k pull-down (see gpio section below) spi_do/gpio11 integrated 10k pull-down (see gpio section below) spi_hold#/gpio31 integrated 10k pull-up ? lpc/ sio/ spi spi_cs#/gpio32 integrated 10k pull-up ? usb_oc9#/slp_s2/ gpm9# integrated 10k pull-down pm2_rg f8h default: pd enabled pwr_btn# integrated 10k pull-up ? pwr_good integrated 10k pull-up ? test[1:0] integrated 10k pull-down ? nb/ power manage- ment test2 integrated 10k pull-down ?
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 48 interface signal name value for integrated / external resistor resistor type register for programming the integrated pu/pd rtcclk integrated 10k pull-up pm_reg: 0eh default: pu enabled. rtc_irq#/gpio69 integrated 10k pull-up (see gpio section below) fanout0/gpio3 integrated 10k pull-up ? fanout1/gpio48 integrated 10k pull-up ? fanout2/gpio49 integrated 10k pull-up ? spi_clk/gpio47 integrated 10k pull-down ? rsmrst# integrated 10k pull-up ? ri#/extevnt0# integrated 10k pull-up pm2_rg f5h default: pu enabled lpc_smi#/extevnt1# integrated 8.2k pull-up pm2_rg f5h default: pu enabled smbalert#/thrmtrip# /gevent2# integrated 10k pull-up pm2_rg f3h default: pu enabled lpc_pme#/gevent3# integrated 10k pull-up pm2_rg f3h default: pu enabled pci_pme#/gevent4# integrated 10k pull-up pm2_rg f4h default: pu enabled s3_state/gevent5# gevent5#: integrated 10k s3_state: push/pull pull-up pm2_rg f4h default: pu enabled usb_oc6#/gevent6# integrated 10k pull-up pm2_rg f4h default: pu enabled usb_oc7#/gevent7# integrated 10k pull-up pm2_rg f4h default: pu enabled wake#/gevent8# integrated 10k pull-up pm2_rg f5h default: pu enabled usb_oc0#/gpm0# integrated 10k pull-up pm2_rg f6h default: pu enabled usb_oc1#/gpm1# integrated 10k pull-up pm2_rg f6h default: pu enabled usb_oc2#/gpm2# integrated 10k pull-up pm2_rg f6h default: pu enabled usb_oc3#/gpm3# integrated 10k pull-up pm2_rg f6h default: pu enabled usb_oc4#/gpm4# integrated 10k pull-up pm2_rg f7h default: pu enabled usb_oc5#/ddr3_rst#/ gpm5# gpm5#: integrated 10k ddr3_rst#: open drain pull-up pm2_rg f7h default: pu not enabled blink/gpm6# integrated 10k pull-up pm2_rg f7h default: pu enabled sys_reset#/gpm7# integrated 10k pull-up pm2_rg f7h default: pu enabled general events/ gpm/ gpio usb_oc8#/az_dock_rs t#/gpm8# integrated 10k pull-up pm2_rg f8h default: pu enabled
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 49 interface signal name value for integrated / external resistor resistor type register for programming the integrated pu/pd usb_oc9#/slp_s2/ gpm9# integrated 10k pull-down pm2_rg f8h default: pd enabled ssmuxsel/sata_is3#/ gpio0 integrated 10k pull-down pm2_rg e0h default: pd enabled rom_cs#/gpio1 integrated 8.2k pull-up pm2_rg e0h default: pu enabled spkr/gpio2 integrated 10k pull-up pm2_rg e0h default: pu/pd not enabled fanout0/gpio3 integrated 10k pull-up pm2_rg e0h default: pu enabled smartvolt/sata_is2#/ gpio4 integrated 8.2k see note pm2_rg e1h default: pu/pd not enabled shutdown#/gpio5/sm artvolt2 integrated 10k see note pm2_rg e1h default: pu/pd not enabled ghi#/sata_is1#/gpio6 integrated 8.2k see note pm2_rg e1h default: pu/pd not enabled wd_pwrgd/gpio7 integrated 10k see note pm2_rg e1h default: pu/pd not enabled ddc1_sda/gpio8 integrated 10k see note pm2_rg e2h default: pu/pd not enabled ddc1_scl/gpio9 integrated 10k see note pm2_rg e2h default: pu/pd not enabled sata_is0#/gpio10 integrated 10k see note pm2_rg e2h default: pu/pd not enabled spi_do/gpio11 integrated 10k pull down pm2_rg e2h default: pd enabled spi_di/gpio12 integrated 10k pull down pm2_rg e3h default: pd enabled lan_rst#/gpio13 integrated 10k see note pm2_rg e3h default: pu/pd not enabled rom_rst#/gpio14 integrated 10k see note pm2_rg e3h default: pu/pd not enabled ide_d0/gpio15 integrated 10k see note pm2_rg e3h default: pu/pd not enabled ide_d1/gpio16 integrated 10k see note pm2_rg e4h default: pu/pd not enabled gpio ide_d2/gpio17 integrated 10k see note pm2_rg e4h default: pu/pd not enabled
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 50 interface signal name value for integrated / external resistor resistor type register for programming the integrated pu/pd ide_d3/gpio18 integrated 10k see note pm2_rg e4h default: pu/pd not enabled ide_d4/gpio19 integrated 10k see note pm2_rg e4h default: pu/pd not enabled ide_d5/gpio20 integrated 10k see note pm2_rg e5h default: pd not enabled ide_d6/gpio21 integrated 10k see note pm2_rg e5h default: pu/pd not enabled ide_d7/gpio22 integrated 10k see note pm2_rg e5h default: pd not enabled ide_d8/gpio23 integrated 10k see note pm2_rg e5h default: pd not enabled ide_d9/gpio24 integrated 10k see note pm2_rg e6h default: pd not enabled ide_d10/gpio25 integrated 10k see note pm2_rg e6h default: pd not enabled ide_d11/gpio26 integrated 10k see note pm2_rg e6h default: pd not enabled ide_d12/gpio27 integrated 10k see note pm2_rg e6h default: pd not enabled ide_d13/gpio28 integrated 10k see note pm2_rg e7h default: pu/pd not enabled ide_d14/gpio29 integrated 10k see note pm2_rg e7h default: pu/pd not enabled ide_d15/gpio30 integrated 10k see note pm2_rg e7h default: pu/pd not enabled spi_hold#/gpio31 integrat ed 10k pull-up pm2_rg e7h default: pu enabled spi_cs#/gpio32 integrated 10k pull-up pm2_rg e8h default: pu enabled inte#/gpio33 integrated 10k pull-up pm2_rg e7h default: pu enabled intf#/gpio34 integrated 8.2k pull-up pm2_rg e7h default: pu enabled intg#/gpio35 integrated 8.2k pull-up pm2_rg e7h default: pu enabled inth#/gpio36 integrated 8.2k pull-up pm2_rg e8h default: pu enabled
?2007- 2008 advanced micro devices, inc. power planes and pin states sb600 databook proprietary page 51 interface signal name value for integrated / external resistor resistor type register for programming the integrated pu/pd dpslp_od#/gpio37 integrated 8.2k see note pm2_rg e8h default: pu/pd not enabled ac_bitclk/gpio38 integrated 10k pull-down pm2_rg e8h default: pd enabled ac_sdout/gpio39 pull down (strap) pull-down pm2_rg e8h default: pd enabled ac_sync/gpio40 integrated 10k pull-down pm2_rg e9h default: pd enabled spdif_out/pciclk7/ gpio41 integrated 10k see note pm2_rg eah. default: pu/pd not enabled acz_sdin[2:0]/ gpio[44:42] integrated 10k pull-down pm2_rg eah default: pd enabled ac_rst#/gpio45 push-pull. no external resistor required. integrated 10k. see note pm2_rg ebh. default: pd not enabled. can be used to keep gpio45 terminated on power up if pin is not used (nc). az_sdin3/gpio46 integrated 50k pull-down pm2_rg ebh. default: pd enabled spi_clk/gpio47 integrated 10k pull-down pm2_rg ebh. default: pd enabled fanout1/gpio48 integrated 10k pull-up pm2_rg ech. default: pu enabled fanout2/gpio49 integrated 10k pull-up pm2_rg ech. default: pu enabled gpio 65:50,67 integrated 10k see note pm2_rg f0h:ech default: pu/pd not enabled llb#/gpio66 integrated 10k pull-up pm2_rg f0h default: pu enabled ldrq1#/gnt5#/gpio68 integrated 15k pull-up pm2_rg f1h default: pu enabled rtc_irq#/gpio69 integrated 10k pull-up pm2_rg f1h default: pu enabled req3#/gpio70 integrated 15k pull-up pm2_rg f1h default: pu enabled req4#/gpio71 integrated 15k pull-up pm2_rg f1h default: pu enabled gnt3#/gpio72 integrated 10k see note pm2_rg f2h default: pu/pd not enabled gnt4#/gpio73 integrated 10k see note pm2_rg f2h default pu/pd not enabled note: the pin has an internal integrated pull-up or pull-down re sistor that is not enabled by default. the pin?s default function does not require a pull-up or pull-down. however, if the pin is used for an alternate function and a pull-up or pull-down is required, the internal resistor can be enabled by the indicated register.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 52 5 functional description 5.1 ehci usb 2.0 and ohci usb 1.1 controllers 5.1.1 usb architecture overview a usb (universal serial bus) host system is co mposed of a number of hardware and software layers. figure 16 illustrates block diagram of the ohci and ehci connectivity to usb ports. figure 5-1: sb600 usb 2.0 system block diagram
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 53 5.1.2 usb power management an advanced power management capability interface compliant with pci bus power management interface specification revision 1.1 is incorporated into the ehci. this interface allows the ehci to be placed in various power management states, offering a variety of power savings for a host system. table 5-1 highlights the ehci support for power managemen t states and features supported for each of the power management states. an ehci implementati on may internally gate-off usb clocks and suspend the usb transceivers (low power consumpti on mode) to provide these power savings. table 5-1: ehci support for power management states pci power management state state required/ optional by spec comments d0 required supported in sb600. fully awake backward compatible state. all logic in full power mode. d1 optional not supported in sb600. usb sleep state with ehci bus ma ster capabilities disabled. all usb ports in suspended state. all logic in low latency power savings mode because of low latency returning to d0 state. d2 optional not supported in sb600. usb sleep state with ehci bus ma ster capabilities disabled. all usb ports in suspended state. d3hot required supported in sb600. deep usb sleep state with ehci bus master capabilities disabled. all usb ports in suspended state. d3cold required supported in sb600. fully asleep backward compatible state. all downstream devices are either suspended or disconnected based on the implementation?s capability to supply downstream port power within the power budget. the functional and wake-up characteristics for the ehci power states are summarized in table 5-2 below. table 5-2: ehci power state summary power state functional characteristics wake-up characteristics (associated enables must be set) d0 ? fully functional ehci device state ? unmasked interrupts are fully functional ? resume detected on suspended port ? connect or disconnect detected on port over current detected on port d1 ? ehci shall preserve pci configuration ? ehci shall preserve usb configuration ? hardware masks functional interrupts ? all ports are disabled or suspended ? resume detected on suspended port ? connect or disconnect detected on port ? over current detected on port d2 ? ehci shall preserve pci configuration ? ehci shall preserve usb configuration ? hardware masks functional interrupts all ports are disabled or suspended ? resume detected on suspended port ? connect or disconnect detected on port ? over current detected on port
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 54 power state functional characteristics wake-up characteristics (associated enables must be set) d3hot ? ehci shall preserve pci configuration ? ehci shall preserve usb configuration ? hardware masks functional interrupts ? all ports are disabled or suspended ? resume detected on suspended port ? connect or disconnect detected on port ? over current detected on port d3cold ? pme context in pci configuration space is preserved ? wake context in ehci memory ? space is preserved ? all ports are disabled or suspended ? resume detected on suspended port ? connect or disconnect detected on port ? over current detected on port 5.2 smi#/sci generation certain system events are routable between smi# or sci. when an event is routed to smi# and occurs, smi# will be asserted by sb600 and the processor will enter smm space. smi# remains active until the eos bit is set. when the eos is set, smi# will be de- asserted for at least 4 pciclk. if the event is routed to sci, then bios can route it to any of the l egacy interrupts (except irq8) or int21 in the case of ioapic. table 5-3: causes of smi# and sci cause sci smi additional enable where reported smi command port yes yes pm x0e, bit 2 pm x0f, bit 2 serr# port yes yes pci config x64, bit 16 pci config x04, bit 30; pm x0f, bit 1 gblrls written to yes yes pm x0e, bit 0 pm x0f ,bit 0 pm timer1 yes yes pm x00, bit 1; pm x08, x09, x0a pm x01, bit 1 pm x00, bit 4 is written 1 yes yes pm x00, bit 4 pm x01, bit 4 irq[15:8] activity yes yes pm x02 pm x05 irq[7:0] activity yes yes pm x03 pm x06 legacy io activity yes yes pm x04 pm x07 io activity yes yes pm x1c, pm xa8 pm x1d, pm xa9 temperature warning yes yes xc50/c51, inde x x03, bit 1 xc50/c51, index x02, bit 1 temperature warning (this input can generate smi# through this set of register) yes yes acpigpe0blk, index 00, bit 9 acpigpe0blk, index 04, bit 9 gevent/gpm inputs yes yes acpigpe0blk, index 00, bits [7:0] for gevent, bits [29, 28, 26, 25, 22:19] for gpm acpigpe0blk, index 04, same bits usb smi# yes yes acpigpe0blk, index 00, bit 8 acpigpe0blk, index 04, bit 8; pm x0f, bit 5 smbus smi# yes yes acpigpe0 blk, index 00, bit 8 acpigpe0blk, index 04, bit 8; pm x0f, bit 4 ac ?97 wake yes yes acpigpe0blk, index 00, bit 12 acpigpe0blk, index 04, bit 12 hdaudio wake yes yes acpigpe0blk, index 00, bit 27 ? usb wake yes yes acpigpe0blk, index 00, bit 11 acpigpe0blk, index 04, bit 11 rtc yes yes rtc_sts rtc_en acpi timer yes yes tmr_sts tmr_en gbl_sts yes yes gbl_sts gbl_en powerbutton yes yes pwrbtn_sts pwrbtn_en
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 55 5.3 lpc isa bridge 5.3.1 lpc interface overview the low pin count (lpc) bus interface is a cost-effi cient, low-speed interface designed to support low- speed legacy (isa, x-bus) devices. the lpc interface essentially eliminates the need of isa and x-bus in the system. a typical setup of the sy stem with lpc interface is shown in figure 5-2 below. here the isa bus is optional. the lpc host controller is typically integrated into the south bridge. it connects to the pci bus on one side and the lpc bus on the other side. lpc host controller lpc bus pci bus isa bus lpc device lpc device figure 5-2: a typical lpc bus system examples of lpc devices include s uper i/o (floppy-disk controller, keyboard controller), bios, audio, and system management controller. figure 5-3 below shows the signals associated with the lpc host controller.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 56 lpc host controller lad[3:0] lframe# lreset# lclk ldrq[1:0]# serirq clkrun# pme# lpcpd# lsmi# optional isa interface ad[31:0] cbe[3:0] frame irdy stop trdy req devsel gnt idsel perr par sd[15:0] sa[15:0] dack[7:0] drq[7:0] iochrdy mcs16 dior diow tc pci interface lpc interface enable_lpc figure 5-3: lpc host controller interfaces and signals note that the isa interface is only used for legacy dma operation. lpc host controller has standard pci interface on one side and lpc interface on the other . some lpc signals are used for power management in mobile systems and are therefore optional. a more detailed description of each signal is given later. the host controller supports memory and io read/ write, dma read/write, bus master memory/io read/write. it supports up to two bus masters and 7 dma channels. a bus master or dma agent uses ldrq pin to assert bus master or dma request. the host controller uses lframe# to indicate the start or termination of a cycle. the following table show s a list of cycles supported by the host controller, initiator, data flow directi on, and their pci counterparts.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 57 table 5-4: lpc cycle list and data direction cycle size (bytes) initiator data direction pci counterpart memory read 1 host p-2-host memread to lpc range memory write 1 host host-2-p memwrit to lpc range i/o read 1 host p-2-host ioread to lpc range i/o write 1 host host-2-p iowrit to lpc range dma read 1,2,4 peripheral host-2-p dma cntrl setup; dma data fetch dma write 1,2,4 peripheral p-2-host dma cntrl setup; dma data store bm memory read 1,2,4 peripheral host-2-p dm a cntrl setup; dma data fetch bm memory write 1,2,4 peripheral p-2-host dm a cntrl setup; dma data store bm i/o read 1,2,4 peripheral host-2 -p dma cntrl setup; io data fetch bm i/o write 1,2,4 peripheral p-2- host dma cntrl setup; io data store the host controller has a serirq (serial irq) pin, wh ich is used by peripherals that require interrupt support. all legacy interrupts are serialized on th is pin, and then decoded by the host controller, and sent to the interrupt controller for processing. please refer to the serial irq specification (rev 5.4) for detailed description on serial irq protocol.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 58 5.3.2 lpc module block diagram figure 5-4: block diagram of lpc module 5.4 real time clock the real time clock (rtc) is used for updating a computer?s time. in addition to that, it also generates interrupts for periodic events and pre-set alarm. t he sb600?s rtc includes a 256-byte cmos ram, which is used to store the configuration of a com puter, such as the number and type of floppy drive, graphics adapter, base memory, checksum value, et c. note that the rtc does make hardware leap year correction. 5.4.1 functional blocks of rtc the internal rtc is made of two parts: one is an analog circuit, powered by a battery vbat, and the other part is a digital circuit, powered by a main power vdd. figure 5-5 shows the block diagram of the internal rtc. configuration register cntrl 32-bit dma buffer ldrq handler master data buffer pci decode state machine protocol state machine misc module pci interface lpc interface isa interface (optional)
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 59 figure 5-5: block diagram of internal rtc 5.5 sata (serial ata) controller the integrated serial ata controller processes host commands and transfers data between the host and serial ata devices. it supports four independent serial ata channels. each channel has its own serial ata bus and supports one serial ata device. for transfer rate, sata controller supports both serial ata generation i (1.5gb/s) and generation ii (3.0gb/s). figure 5-6 below is a diagram for the sata block.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 60 512-byte reception fifo 512-byte transmission fifo 64-bit pci/b-link interface data to be read data to be written serdes interface phy link host transport clock asicclk0 port0 link clock blink clock port0 port3 port2 port1 ahci global control register & port mapping asicclk2 asicclk3 asicclk1 figure 5-6: block diagram for the sata module 5.6 ac ?97 controller a standard ac-link digital serial interface is used in the sb600 ac ?97 controller. this bi-directional time division multiplex serial pcm digital stream runs at a fixed rate with each frame being transmitted at 48 khz. the interface for the sb600 ac ?97 controller consists of six pins that transfer data in both directions. data is transferred to the ac ?97 codec through the ac_sdout port for audio playback, register access request, and modem data out. in the opposite direction, data is transferred from the ac ?97 codec to the sb600 ac ?97 controller through the acz_sdin for audio record, register status read back, and modem data in. the controller supports up to three ac ?97 codecs. table 5-5: pin definitions pin name i/o purpose ac_bitclk in serial data transmission clock at 12.288mhz acz_sdin0 in data to the ac ?97 controller from primary codec acz_sdin1 in data to the ac ?97 contro ller from a secondary codec (slave 1) acz_sdin2 in data to the ac ?97 contro ller from a secondary codec (slave 2) ac_sdout out data from the ac ?97 controller ac_sync out synchronization signal at 48khz ac_rst# out reset to the codec(s)
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 61 5.6.1 output data stream the output data streams refer to the data going from the ac ?97 controller to the codec(s). a timing diagram of the 13 slots is shown below. table 5-6 describes the use of each one of the slots. each new bit position is presented into the ac-link at the rising edge of the ac_ bitclk . the data is subsequently sampled by the codec on the following falling edge of the ac_bitclk. figure 5-7: aclink ac_sdout serial stream table 5-6: ac_sdout slots definitions sdata_out slots purpose slot 0 tag: bit 15: identity the valid ity of the entire aud io output frame bit 14:3: identity the validity of each slot bit 2 : reserved bit 1:0: target codec id of the current frame slot 1 command address bit 19: identity codec regi ster read/write operation - 0 is write bit 18:12 : contains the target codec register address bit 11:0 : reserved slot 2 command data 19:4 data to be transferred to the register address identified by slot 1 in case of a write operation 3:0 reserved slot 3 pcm playback left channel slot 4 pcm playback right channel slot 5 modem dac data slot 6 pcm center slot 7 pcm left surround sound slot 8 pcm right surround sound slot 9 pcm lfe slot 10 modem 2 dac data or pcm left for 96 mhz audio support slot 11 hand set data (hset dac) or pcm right for 96 mhz audio support slot 12 modem gpio control data or pcm center data for 96 mhz audio support 5.6.2 input data stream the input data stream, acz_sdin, refers to the data goi ng from the codec(s) to the ac ?97 controller. a timing diagram of the 13 slots is shown in figure 5-8 . table 5-7 describes the use of each one of the slots. each new bit position is presented into the ac link at the rising edge of the bit_clk. the data is subsequently sampled by the ac ?97 controlle r during the following falling edge of the bit_clk.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 62 figure 5-8: aclink acz_ sdin serial stream table 5-7: acz_sdin slots definitions sdata_in slots purpose slot 0 tag bit 15 : codec ready bit 14:3 : identity the validity of each slot bit 2:0 : reserved slot 1 status address bit 19 : reserved bit 18:12 : echoes the command address slot bit 11:2 : slot request for supporting non-48khz audio streams bit 1:0 : reserved slot 2 status data contains the register data of the re gister address indicated in slot 1 slot 3 pcm record left channel left audio sample from adc slot 4 pcm record right channel right audio sample from adc slot 5 modem adc data modem audio sample from modem adc slot 6 mic adc microphone data slot 7-9 reserved - not used in 2.1 spec slot 10 modem 2 adc data modem audio sample from modem adc slot 11 hset dac hand set data slot 12 modem gpio status contains current status of the gpio pins on the codec 5.6.3 ac '97 controller-codec(s) connections the five ac link pins on each codec are required to be connected with the ac ?97 controller. figure 5-9 shows a simple connection between a single codec (eit her ac ?97 or amc97) and the ac ?97 controller.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 63 ac97 digital controller ac97 codec ac_bitclk ac_sync ac_sdout ac_rst# ac_sdin host bus figure 5-9: single ac ?97 codec connection for a multiple codec configuration (see figure 5-10 ), one of the codecs will act as the primary unit and provide the central master clock to the system. in th is configuration, all three ac ?97 codecs share the serial output data from the digital controller. each codec will be responsible for parsing out the intended data from the stream based on the time slots. all code cs can send in data to the digital controller at the same time provided they do not share the same time slot.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 64 ac97 digital controller primary ac97 codec ac_bitclk ac_sync ac_sdout ac_rst# host bus secondary ac97 codec secondary ac97 codec ac_sdin1 ac_sdin2 ac_sdin0 figure 5-10: multiple ac ?97 codec connection
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 65 5.7 high definition audio intel? high definition (hd) audio is the next-genera tion pc audio technology intended for replacing the ac ?97. the primary goal for developing hd audio is to create a uniform programming interface and to provide capabilities beyond those suppo rted by the ac ?97. it is not intended to be backward compatible with the ac ?97. the link protocols and operations of these two standards are not compatible, which means ac ?97 and hd audio codecs cannot be mixed on the same link. the sb600 supports hd audio with a separate engine from that of the ac ?97. also, the physical codec buses are separate, so that the ac ?97 and hd engine s can operate simultaneously. this allows mixed system configurations, supporting, for example, an hd audio interface together with an ac ?97 modem. 5.7.1 hd audio codec connections figure 5-11 below shows the hd audio interface con nections to the hd audio codecs. the ac ?97 audio interface shares pins sdin[2:0] with the hd audio interface, and together with the dedicated sdin3 pin, they support up to 4 hd audio codecs. those shar ed pins on the sb600 are named acz_sdin[2:0] to indicate support for both interfaces and, together wi th az_sdin3, they act as data input for the hd audio interface. figure 5-11 shows the signals on both interfaces and their interrelationships. ac 97 sync / bitclk /rst# sdin0 sdin1 sdin2 hdaudio sync/bitclk/rst# hd audio sdout sdout hd audio sdin3 ac 97 figure 5-11: hd audio codec connections 5.7.2 hd audio and ac ?97 codec conn ections in mixed configurations sb600 also allows mixing ac? 97 and hd audio codecs in a system. as discussed in section 3.15, az_sdin3 can only be connected to an hd audio co dec, while acz_sdin[2:0] can be connected to either an ac? 97 codec (audio / modem) or hd audio codec. figure 5-12 and figure 5-13 below show some possible configurations combining hd a udio and ac? 97 codecs on the same system.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 66 figure 5-12: hd audio and ac ?97 codec connec tions for mixed configurations
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 67 r14 33 r15 33 hd audio cnr j2 amp_650090-6 b32 b31 b30 a31 a30 a29 a28 ac97_bitclk ac97_sdat_out ac97_sy nc ac97_sdat_in0 ac97_sdat_in1 ac97_sdat_in2 ac97_rst# r8 33 sb600 u1d k2 n2 m2 l3 k3 l1 l2 l4 j2 j4 m3 l5 t1 az_sdin3/gpio46 az_bitclk az_sdout az_sy nc az_rst# ac_bitclk/gpio38 ac_sdout/gpio39 acz_sdin0/gpio42 acz_sdin1/gpio43 acz_sdin2/gpio44 ac_sync/gpio40 ac_rst#/gpio45 spdif_out/pciclk7/gpio41 r9 33 r10 33 r4 33 r5 33 r7 33 r6 33 r3 33 r2 33 r1 33 ac97 cnr j1 amp_650090-6 b32 b31 b30 a31 a30 a29 a28 ac97_bitclk ac97_sdat_out ac97_sy nc ac97_sdat_in0 ac97_sdat_in1 ac97_sdat_in2 ac97_rst# hd audio codec u2 alc880 5 6 8 10 11 sdata_out bit_clk sdata_in sy nc reset# r12 33 r13 33 r11 33 instal only one res depending on which sdin is required figure 5-13: schematic for hd audio and ac ?97 codec connections in a mixed configuration install only one resistor, depending on which sdin is required.
?2007- 2008 advanced micro devices, inc. functional description sb600 databook proprietary page 68 5.8 general events and gpios table 5-8: smi, sci, and wake event support by gpio and general event pins pin name smi event sci event wake event gpio [0,2] x x x gpm [0:9] x x x gevents [2:8] x x x external events [0:1] x x x the following table shows the state of the gpio and gevent pins in di fferent acpi states. note that even if some gpios are in the s5 domain, its functionality may not be maintained in the s5 state. table 5-9: functionality of the general events and gpios across acpi states gpio and g-events functionality across acpi states gpio / gevent s0/s1 s2/s3 s4/s5 g3 extevent0#, gevent# [7:2] maintain state undefined extevent1# maintain state undefined gpm [9:0] maintain state undefined gpoc [1:0] maintain state undefined gpoc [3:2] maintain state undefined gpio [73:0] maintain state undefined note: except for gpio1, all other gpio and gpm pins are software configurable to assume alternate functions . please refer to the gpio section in the sb600 register reference guide for information on how to configure the gpio pins to alternate functions.
?2007- 2008 advanced micro devices, inc. system clock specifications sb600 databook proprietary page 69 6 system clock specifications 6.1 system clock descriptions table 6-1: sb600 system clock descriptions clock domain frequency source usage pcie_rclkp, pcie_rclkn 100mhz main clock generator (external clock) for pcie differential input sata_x1, sata_x2 25mhz 25mhz crystal for sata controllers x1, x2 32khz 32khz crystal for rtc 14m_osc 14.31818mhz main clock generator (external clock) for timer usbclk 48mhz 48mhz osc or internal usb 48mhz pll for usb controllers and hd audio ac_bitclk 12.288mhz ac ?97 codec for ac ?97 link generated by ac?97 6.2 system clock input frequency specifications table 6-2: sb600 system clock input frequency specifications clock frequency min max 14m_osc 14.31818 mhz 14.315603 mhz 14.320757 mhz usbclk 48.000 mhz 47.995 mhz 48.005 mhz sata_x1, sata_x2 25.000 mhz 24.997 mhz 25.005 mhz ac_bitclk 12.288mhz the clock is supplied to sb by the external codec. 12.288mhz is its typical frequency. 6.3 system clock ac specifications table 6-3 to table 6-8 list all the ac specifications of sb600 cloc ks at specific vih/vil combinations. the figure below illustrates the timing labels that appear in those tables.
?2007- 2008 advanced micro devices, inc. system clock specifications sb600 databook proprietary page 70 t62 t63 t64 t65 t 61 v ih v il figure 6-1: timing labels for ac specifications of the sb600 clocks table 6-3: 14 mhz osc reference clock ac specifications 14 mhz osc reference clock symbol parameter min max units note t61 clock period 69.829 69.854 ns 1 t62 clock/data rise time 1 1.5 ns t63 clock/data fall time 1 2 ns t64 clock high period 30 38 ns t65 clock low period 30 38 ns 2 - cycle to cycle jitter - 300 ps - - duty cycle 40 60 % - notes: 1 clock frequency tolerance is +/- 180 ppm 2 vil= 0.4v ; vilmax = 0.6v and vilmin = 0v vih = 2.4v; vihmax =vddr and vihmin = 2.0v table 6-4: 48mhz usb/si o clock ac specifications 48 mhz usb / sio clock symbol parameter min max units note t61 clock period 20.831 20.836 ns 1 t62 clock/data rise time 0.5 1.5 ns t63 clock/data fall time 0.5 1.5 ns t64 clock high period 8.8 11 ns t65 clock low period 7.7 10 ns 2 - max jitter - 130 ps - - duty cycle 45 55 % - notes: 1 clock frequency tolerance is +/- 100 ppm 2 vil= 0.4v ; vilmax = 0.6v and vilmin = 0v vih = 2.4v; vihmax=v ddr and vihmin = 2.0v
?2007- 2008 advanced micro devices, inc. system clock specifications sb600 databook proprietary page 71 table 6-5: rtc x1 clock ac specifications rtc x1 clock symbol parameter min max units note t61 clock period typical at 32.7 khz 1 t62 clock/data rise time 0.5 5 ns t63 clock/data fall time 0.5 5 ns t64 clock high period 13 17 ns t65 clock low period 13 17 ns 2 - cycle to cycle jitter 10 ns - duty cycle 45 55 % - frequency tolerance -20 20 ppm notes 1 min/max specifications depend on accuracy of the crystal used. 2 vil= 0.25v ; vilmax = 250mv and vilmin = 0v vih = 0.75v; vihmax=1v and vihmin = 750mv table 6-6: lpc clock ac specifications lpc clock symbol parameter min max units note t61 clock period 30 33.3 ns - t62 clock/data rise time - 3 ns - t63 clock/data fall time - 3 ns - t64 clock high period 12 - ns - t65 clock low period 12 - ns - table 6-7: pci clock ac specifications pci clock (8 clocks) pciclk[7:0] symbol parameter min max units note t61 clock period 30 33.3 ns - t62 clock/data rise time - 3.0 ns - t63 clock/data fall time - 3.0 ns - t64 clock high period 12 - ns - t65 clock low period 12 - ns -
?2007- 2008 advanced micro devices, inc. system clock specifications sb600 databook proprietary page 72 table 6-8: ac 97 clock ac specifications ac97 clock symbol parameter min max units note t61 clock period typical at 813.80 ns 1 t62 clock/data rise time 2.0 4.0 ns - t63 clock/data fall time 2.0 4.0 ns - t64 clock high period 32.56 48.84 ns - t65 clock low period 32.56 48.84 ns - - max jitter - 750 ps - note 1: nominal clock frequency is 12.288mhz.
?2007- 2008 advanced micro devices, inc. states of power rails during acpi s1 to s5 states sb600 databook proprietary page 73 7 states of power rails during acpi s1 to s5 states sb600 supports the acpi states s1 to s5. table 7-1 below shows the expected state of each power rail during these power states. table 7-1: state of each power rail during acpi s1 to s5 states acpi state pin name schematic signal s0 s1/s2 s3 s4/s5 vddq 3.3v i/o power +3.3v +3.3v 0v 0v vdd_core vcore_1.8 +1.2v +1.2v 0v 0v s5_1.2v s5 power +1.2v +1.2v +1.2v +1.2v cpu_pwr cpu power cpu cpu 0v 0v avddc analog usb 2.0 pwr +3.3v +3.3v +3.3v +3.3v or 0v avddtx[3:0] /avddrx[3:0] usb_avdd +3.3v +3.3v +3.3v +3.3v or 0v usb_phy_1.2v usb phy digital power +1.2v +1.2v +1.2v +1.2v or 0v avdd_sata sata power +1.2v +1.2v 0v 0v pllvdd_sata sata pll power +1.2v +1.2v 0v 0v xtlvdd_sata sata xtal power +3.3v +3.3v 0v 0v v5_vref +5v ref voltage +5.0v +5.0v 0v 0v avddck_3.3v pll analog power +3.3v +3.3v 0v 0v avddck_1.2v pll digital power +1.2v +1.2v 0v 0v s5_3.3v s5 i/o power +3 .3v +3.3v +3.3v +3.3v pcie_pvdd pci express pll power +1.2v +1.2v 0v 0v pcie_vddr pci express i/o power +1.2v +1.2v 0v 0v slp_s3# slp_s3# +3.3v +3.3v 0v 0v slp_s5# slp_s5# +3.3 v +3.3v +3.3v 0v pwr_good sb_pwrok +3.3v +3.3v 0v 0v sus_stat# sus_stat# 0v 0v 0v 0v rsmrst# rsmrst# +3.3v +3.3v +3.3v +3.3v
?2007- 2008 advanced micro devices, inc. electrical characteristics sb600 databook proprietary page 74 8 electrical characteristics note: values quoted in this section are preliminary and require further verification. 8.1 absolute maximum ratings table 8-1 specifies the absolute maximum rati ngs that should never be exceeded. exceeding the specified absolute maximum ratings may damage the asic. these ratings are guidelines for absolute worst case operating conditions and should not to be interpreted as recommended operating condition. table 8-1: absolute maximum rating signal name maximum limits (v) with respect to description vdd_[12:1] -0.5 to 1.32 vss core power vddq_[28:1] -0.5 to 3.66 vss 3.3v i/o power s5_1.2v_[4:1] -0.5 to 1.32 vss 1.2v s5 power s5_3.3v_[6:1] -0.5 to 3.66 vss 3.3v s5 power avddck_3.3v -0.5 to 3.66 avssck 3.3v power for analog plls avddck_1.2v -0.5 to 1.32 avssck 1.2v power for analog plls pcie_pvdd -0.5 to 1.32 pcie_vss a-link express ii pll power pcie_vddr[13:1] -0.5 to 1.32 pcie _vss a-link express ii analog power avdd_sata[15:1] -0.5 to 1.32 avss_sata sata analog power pllvdd_sata_[2:1] -0.5 to 1.32 avss_sata sata pll power xtlvdd_sata -0.5 to 1.32 avss_sata sata xtal power vbat -0.5 - 3.6v bat rtc_gnd rtc backup power avddc -0.5 to 3.66 avssc analog power for usb phy pll avddrx[4:0] -0.5 to 3.66 avss_usb analog power for usb phy rx avddtx[4:0] -0.5 to 3.66 avss_usb analog power for usb phy tx usb_phy_1.2v[5:1] -0.5 to 1.32 avss_usb 1.2v usb phy standby power v5_vref -0.5 to 5.5 vss 5v refe rence voltage for pci interface any 3.3v input signal -0.5 to 3.66 vss any 3,3v 5v tolerant input signal -05 to vref+0.5 vss see section 3 for signal names 8.2 functional operating range use typical values between +/-5% on all input signals.
?2007- 2008 advanced micro devices, inc. electrical characteristics sb600 databook proprietary page 75 8.3 dc characteristics table 8-2: dc characteristic for power supplies to the sb600 signal name description min. voltage typical voltage max. voltage unit avddck_1.2v core pll digital power 1.14 1.2v 1.26 v pcie_pvdd a-link express ii pll power 1.14 1.2v 1.26 v pcie_vddr[13:1] a-link express ii power 1.14 1.2v 1.26 v pllvdd_sata[2:1] sata p ll power 1.14 1.2v 1.26 v avdd_sata[15:1] sata analog power 1.14 1.2v 1.26 v s5_1.2v standby powe r 1.14 1.2v 1.26 v usb_phy_1.2v[5:1] usb phy standby power 1.14 1.2v 1.26 v vdd[12:1] core volt age 1.14 1.2v 1.26 v xtlvdd_sata sata xtal power 3.135 3.3v 3.465 v vbat rtc backup power 2.5* 3.3 3.6 v avddck_3.3v core pll analog power 3.135 3.3v 3.465 v avddc analog power for usb phy pll 3.135 3.3v 3.465 v avddrx[4:0] analog power for usb phy 3.135 3.3v 3.465 v avddtx[4:0] analog power for usb phy 3.135 3.3v 3.465 v s5_3.3v[6:1] core standb y power 3.135 3.3v 3.465 v vddq[28:1] i/o powe r 3.135 3.3v 3.465 v v5_vref 5v reference voltage 4.75 5v 5.25 v * note: for vbat below 2.5v, the battery-low error will occur. at 2.0v, the cmos content may be lost. table 8-3: dc characteristics for interfaces on the sb600 symbol parameter minimum maximum unit condition gpio vdd power supply 3.135 3.46 v vil input low voltage -0.5 1.3 v vih input high voltage 1.8 vdd v vol output low voltage 0.4 v iol = 8.0ma voh output high voltage 2.4 v ioh = 8.0ma ili input leakage current +/-10 a cin input capacitance 10 pf pci vdd power supply 3.135 3.46 v v5ref reference 3.135 5.25 v vil input low threshold -0.5 0.3vdd v vih input high threshold 0.5vdd v5ref v vol output low voltage 0.4 v iol = 4.0ma voh output high voltage 2.4 v ioh=-4.0ma ili input leakage current +/-10 a cin input capacitance 10 pf ide
?2007- 2008 advanced micro devices, inc. electrical characteristics sb600 databook proprietary page 76 symbol parameter minimum maximum unit condition vdd power supply ( driver & receiver) 3.135 3.46 v vih input high voltage 0.5vdd v5ref v vil input low voltage -0.5 03vdd v vol output low voltage 0.662 v iol= 6ma voh output high voltage vdd-0.66 v ioh=6ma ili input leakage current +/-10 a pull-up & pull-down resistors disabled cin input capacitance 10 pf cpu vcpu_io cpu io voltage - - v vil input low voltage -0.15 0.58vcpu_io v vih input high voltage 0.73vcpu_io vcpu_io v vol output low voltage -0. 15 0.25vcpu_io v iol = 4.0ma voh output high voltage / internal pull-up voltage vcpu_io v ili input leakage current +/-10 a cin input capacitance 10 pf lpc see values for the pci pins. ac97 ac_bitclk?see values for ide pins. ac_sdout, ac_stnc, spif_out?see values for pci pins. acz_sdin[2:0], ac_rst#?s ee values for gpio pins. table 8-4: gpio/gevent output dc characteristics voh vol pin name parameter minimum maximum output high voltage 2.4 v ? output low voltage ? 0.4 v output drive all gpio and gevent pins listed in table 8-5 output drive 8 ma table 8-5: gpio/gevent i nput dc characteristics vil(v) vih (v) pin name voltage min max min max ssmuxsel / sata_is3#/gpio0 3.3v (5v tolerance) -0.5 0.3* vddq 0.7*vddq v5_ref + 0.25 rom_cs#/gpio1 3.3v (5v tolerance) -0 .5 0.3* vddq 0.7*vddq v5_ref + 0.25 spkr/gpio2 3.3v (5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 fanout0/gpio3 3.3v (5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 smartvolt/ sata_is2#/gpio4 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vddq v5_ref + 0.25 shutdown#/ gpio5/smartvolt2 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vddq v5_ref + 0.25 ghi#/ sata_is1#/gpio6 3.3v(5v tolerance) -0.5 0.3* vddq 0.7* vddq v5_ref + 0.25 wd_pwrgd/ gpio7 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 ddc1_sda/gpio8 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vddq v5_ref + 0.25
?2007- 2008 advanced micro devices, inc. electrical characteristics sb600 databook proprietary page 77 vil(v) vih (v) pin name voltage min max min max ddc1_scl/gpio9 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vddq v5_ref + 0.25 sata_is0#/gpio10 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 spi_do/gpio11 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 spi_di/gpio12 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 lan_rst#/gpio13 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 rom_rst#/ gpio14 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 ide_d[15:0]/gpio[30:15] 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vddq v5_ref + 0.25 spi_hold#/ gpio31 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 spi_cs#/gpio32 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 inte#/gpio33 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 intf#/gpio34 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 intg#/gpio35 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 inth#/gpio36 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 dpslp_od#/ gpio37 3.3v(5v tolerance) -0 .5 0.3* vddq 0.7*vddq v5_ref + 0.25 ac_bitclk/ gpio38 3.3v(5v tolerance) -0 .5 0.3* vddq 0.7*vddq v5_ref + 0.25 ac_sdout/ gpio39 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 ac_sync/gpio40 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 spdif_out/ pciclk7/gpio41 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vddq v5_ref + 0.25 acz_sdin0/ gpio42 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 acz_sdin1/ gpio43 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 acz_sdin2/ gpio44 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 ac_rst#/gpio45 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 az_sdin3/gpio46 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 spi_clk/gpio47 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 fanout1/gpio48 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 fanout2/gpio49 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 fanin0/gpio50 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 fanin1/gpio51 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 fanin2/gpio52 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 vin[7:0]/gpio[60:53] 3.3v -0.5 0. 3* vddq 0.7*vddq vddq + 0.25 tempin[2:0]/gpio[63:61] 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 tempin3/talert#/gpio 64 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 bmreq#/req5#/ gpio65 3.3v -0.5 0. 3* vddq 0.7*vddq vddq + 0.25 llb#/gpio66 s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 sata_act#/ gpio67 3.3v -0.5 0.3* vddq 0.7*vddq vddq + 0.25 ldrq1#/gnt5#/ gpio68 3.3v(5v tolerance) -0 .5 0.3* vddq 0.7*vddq v5_ref + 0.25
?2007- 2008 advanced micro devices, inc. electrical characteristics sb600 databook proprietary page 78 vil(v) vih (v) pin name voltage min max min max rtc_irq#/gpio69 s5_3.3v/vbat -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 req3#/gpio70 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 req4#/gpio71 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 gnt3#/gpio72 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 gnt4#/gpio73 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 usb_oc[4:0]#/gpm[4:0]# s5_3. 3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 usb_oc5#/ddr3_rst#/ gpm5# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 blink/gpm6# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 sys_reset#/ gpm7# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 usb_oc8#/ az_dock_rst#/ gpm8# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 usb_oc9#/slp_s2/gpm 9# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 ri#/extevent0# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 lpc_smi#/ extevent1# 3.3v(5v tolerance) -0 .5 0.3* vddq 0.7* vddq v5_ref + 0.25 smbalert#/thrmtrip# /gevent2# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 lpc_pme#/ gevent3# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 pci_pme#/ gevent4# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 s3_state/ gevent5# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 usb_oc6#/ gevent6# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 usb_oc7#/ gevent7# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 wake#/gevent8# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 scl0/gpoc0# 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 sda0/gpoc1# 3.3v(5v tolerance) -0.5 0.3* vddq 0.7*vd dq v5_ref + 0.25 scl1/gpoc2# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25 sda1/gpoc3# s5_3.3v -0.5 0.3* s5_3.3v 0.7* s5_3.3v s5_3.3v + 0.25
?2007- 2008 advanced micro devices, inc. electrical characteristics sb600 databook proprietary page 79 8.4 rtc battery curr ent consumption the rtc battery current consum ption is measured as follows: table 8-6: rtc battery current consumption rtc battery current power states typical maximum g3 (off), s0-s5 < 0.5 a < 3 a rtc battery life is calculated using the rated capa city of the battery and the measured maximum current consumption. rtc battery?s are normally rated for 170 mah and the worst case current consumption for the sb600 is 3.0 a. thus, the expected mi nimum life of battery will be as follows: 170,000 a / 3 a = 56,667 h = 6.5 years
?2007- 2008 advanced micro devices, inc. power requirements sb600 databook proprietary page 80 9 power requirements table 9-3 to table 9-5 indicate the power activity of the sb600 re v a13 for each of configurations 1 to 7, described in table 9-1 below. configuration 1 gives measurements for idle status on a mobile system. configuration 2, 4, and 6 give measurements of minimu m activity with system idle status for specific hardware setups, and configuration 3, 5, and 7 give measurements of maximum power activity for the same setups. measurements are divided into two categories: average power dissipation ?calculated average power based on sample readings taken every 2 seconds during the test. maximum (peak) power dissipation ?measured maximum power reading recorded among the sample readings. in each category, two subcategories are used to reco rd power data: normal activity indicates power recording with system running normally, and maximum activity shows sb600?s maximum power affordability. all test measurements are taken at 25 o c with no cpu airflow, and the m easurement tolerance is 5%. note: a heat sink is required for the sb600 if the case temperature exceeds 105 oc. the case temperature should be measured using a thermal couple diode connected to the centre at the top of the sb600 with the system in the enclosed production ca se and configured with all internal and external devices enabled. application software or a test utility should be used to exercise all devices and interfaces connected to the sb600 when measuring the case temperature. more details on how to select the correct heat sink can be found in the sb600 thermal design guide (tdg-sb600-01) that is available at amd?s partner resource center. table 9-1: configuration set up for sb600 power activity test configuration # hardware system activity 1 usb and sata disabled in bios 1 hdd ide drive connected enabled a-link x2 windows idle for mobile 2 windows idle for mobile/desktop 3 usb and sata controllers* enabled in bios 2 usb 1.1 devices connected to the system 1ide odd drive + 1x1.5g sata drive connected enabled a-link x2 third party and internal amd software used to create maximum activity on a mobile system. 4 windows idle for mobile. 5 usb and sata controllers * enabled in bios 4 usb 2.0 devices (2xusb1.1 and 2xusb 2.0)connected to the system 1 ide odd drive + 1x1.5g sata drive connected enabled a-link x2. third party and internal amd software used to create maximum activity on a mobile system. 6 windows idle for desktop. 7 usb and sata controllers * enabled in bios 4 usb 2.0 devices (2xusb1.1 and 2xusb 2.0)connected to the system 1 ide odd drive + 1x1.5g sata drive connected enabled a-link x2 1 external pci(lan) connected third party and internal amd software used to create maximum activity on a desktop system. note: * the sata controller supports 4 ports, but only one port is active.
?2007- 2008 advanced micro devices, inc. power requirements sb600 databook proprietary page 81 table 9-2: power activity under configuration 1 average power (ma) maximum power (ma) s0 1.2v vdd 185.61 189.7 pcie_pvdd 28.2 28.49 pcie_vddr 177.25 177.55 pllvdd_sata 4.25 4.41 avdd_sata 3.13 3.32 avddck_1.2v 31.67 31.91 total s0_1.2v 430.11 435.38 s5 1.2v s5_1.2v 17.64 21.81 usb_phy_1.2v 0.23 2.42 total s5 1.2v 17.87 24.23 s0 3.3v avddc 0.12 0.46 xtlvdd_sata 0 0 vddq 81.01 85.17 avdd 0 0.17 total s0_3.3 v 81.13 85.8 s5 3.3v s5_3.3v 6.88 8.94 avddtx 0.1 0.42 avddrx 0 0.18 avddck_3.3v 4.68 4.85 total s5 3.3v 11.66 14.39 other voltages cpu_pwr (1.05v) 0.11 2.2 v5_vref (5v) 0.15 2.27 total current (ma) 541.03 564.27 total power (w) 0.845 0.868 case temp (oc) 28.4 28.5 table 9-3: power activity under configuration 2 and 3 average power (ma) maximum power (ma) minimum activity maximum activity minimum activity maximum activity s0 1.2v vdd 301.3 306.43 312.23 314.71 pcie_pvdd 27.83 28.04 28.38 28.6 pcie_vddr 252.46 252.51 252.86 252.88 pllvdd_sata 53.1 53.56 54.08 54.1 avdd_sata 75.06 75.29 75.79 75.84 avddck_1.2v 31.5 31.46 31.91 32.03 total s0_1.2v 741.25 747.29 755.25 758.16 s5 1.2v s5_1.2v 59.77 59.88 66.71 67.79 usb_phy_1.2v 5.25 10.56 17.31 18.21 total s5 1.2v 65.02 70.44 84.02 86 s0 3.3v avddc 9.86 10.39 10.38 10.48
?2007- 2008 advanced micro devices, inc. power requirements sb600 databook proprietary page 82 average power (ma) maximum power (ma) minimum activity maximum activity minimum activity maximum activity xtlvdd_sata 1.11 1.36 1.43 1.45 vddq 80.32 81. 41 88.88 89.37 avdd 0 0.02 0.35 0.36 total s0_3.3 v 91.29 93.18 101.04 101.66 s5 3.3v s5_3.3v 6.59 6.55 11.33 11.5 avddtx 7.73 8.93 8.28 11.55 avddrx 15.6 15.87 16.05 16.12 avddck_3.3v 4.7 4.97 5 5.06 total s5 3.3v 34.62 36.32 40.66 44.23 other voltages cpu_pwr (1.05v) 0.07 0.09 4.67 4.74 v5_vref (5v) 0.01 0.14 4.5 4.71 total current (ma) 932.26 947.46 990.14 999.5 total power (w) 1.39 1.4 1.45 1.47 case temp (oc) 30.4 30.9 30.9 31 table 9-4: power activity under configuration 4 and 5 average power (ma) maximum power (ma) minimum activity maximum activity minimum activity maximum activity s0 1.2v vdd 307.63 315.63 317.67 325.11 pcie_pvdd 28.23 28.82 28.33 28.34 pcie_vddr 252.44 252.45 252.76 252.82 pllvdd_sata 53.31 53.39 54.09 54.1 avdd_sata 75.26 75.78 75.78 75.79 avddck_1.2v 31.39 31.27 31.91 31.97 total s0_1.2v 748.26 757.34 760.54 768.13 s5 1.2v s5_1.2v 67.6 67.61 69.6 73.87 usb_phy_1.2v 27.59 27.96 32 32.61 95.19 95.57 101.6 106.48 s0 3.3v avddc 10.08 10.43 10.43 10.43 xtlvdd_sata 1.34 1.39 1.41 1.42 vddq 80.93 83. 53 88.13 89.09 avdd 0.01 0.05 0.34 0.36 total s0_3.3 v 92.36 95.4 100.31 101.3 s5 3.3v s5_3.3v 9.29 9.66 11.4 11.52 avddtx 50.76 52.46 51.45 57.34 avddrx 57.82 58.01 58.35 58.91 avddck_3.3v 4.27 4.45 5.15 5.2 total s5 3.3v 122.14 124.58 126.35 132.97 other voltages cpu_pwr (1.05v) 0.19 0.19 4.38 4.58 v5_vref (5v) 0.17 0.19 4.43 4.78
?2007- 2008 advanced micro devices, inc. power requirements sb600 databook proprietary page 83 average power (ma) maximum power (ma) minimum activity maximum activity minimum activity maximum activity total current (ma) 1058.31 1073.27 1097.61 1118.24 total power (w) 1.72 1.74 1.76 1.78 case temp (oc) 31.4 31.6 31.5 31.7 table 9-5: power activity under configuration 6 and 7 average power (ma) maximum power (ma) minimum activity maximum activity minimum activity maximum activity s0 1.2v vdd 310.92 322.78 332.19 334.19 pcie_pvdd 27.63 27.91 28.28 28.37 pcie_vddr 250.2 250.28 250.58 250.59 pllvdd_sata 53.37 53.56 54.02 54.12 avdd_sata 90.04 90.43 90.51 90.52 avddck_1.2v 31.57 31.57 31.87 31.92 total s0_1.2v 763.73 776.53 787.45 789.71 s5 1.2v s5_1.2v 65.14 65.85 73.07 73.91 usb_phy_1.2v 47.17 45.86 53.32 54.1 112.31 111.71 126.39 128.01 s0 3.3v avddc 10.2 10.22 10.62 10.66 xtlvdd_sata 1.33 1.37 1.4 1.45 vddq 83.64 84. 64 95.66 96.13 avdd 0 0.04 0.38 0.39 total s0_3.3 v 95.17 96.27 108.06 108.63 s5 3.3v s5_3.3v 6.92 7.97 11.23 12.78 avddtx 110.02 110.43 110.78 112.59 avddrx 119.95 120.08 120.49 121.17 avddck_3.3v 4.45 4.72 5.08 5.18 total s5 3.3v 241.34 243.2 247.58 251.72 other voltages cpu_pwr (1.05v) 0.17 0.25 4.31 4.81 v5_vref (5v) 0.15 0.36 4.95 5.14 total current (ma) 1212.87 1228.32 1278.74 1288.02 total power (w) 2.17 2.18 2.22 2.46 case temp (oc) 32.6 32.8 32.7 33 table 9-6 below lists results of power consumption measurements for a fully loaded system (testing configuration: 4 x sata 3.0g drives, 9x usb devices, 2 x ide devices , 1 floppy drive, 2x pci add on cards, on board ac97 audio enabled).
?2007- 2008 advanced micro devices, inc. power requirements sb600 databook proprietary page 84 table 9-6: power activity for sb600 under a fully loaded system configuration average power (ma) maximum power (ma) normal activity maximum activity minimum activity maximum activity s3 s5 s0 1.2v vdd 403.45 406.39 414.93 423.12 0 0 pcie_pvdd 27.65 27.72 27.92 27.86 0 0 pcie_vddr 388.16 390.71 391.01 390.82 0 0 pllvdd_sata 53.77 54.04 54.33 54.17 0 0 avdd_sata 242.94 243.86 244.62 244.53 0 0 avddck_1.2v 31.16 31. 25 31.41 31.28 0 0 total s0_1.2v 1147.13 1153.97 1164.22 1171.78 0 0 s5 1.2v s5_1.2v 66.27 66.4 67.46 70.73 1.25 1.2 usb_phy_1.2v 75.41 75.44 76.42 77.55 0 0 total s5 1.2v 141.68 141.84 143.88 148.28 1.25 1.2 s0 3.3v avddc 10.44 10.44 10.47 10.71 0 0 xtlvdd_sata 1.03 1.04 1.05 1.19 0 0 vddq 96.06 96.77 100.36 117.6 0 0 avdd 0.01 0.03 0.07 0.19 0 0 total s0_3.3 v 107.54 108.28 111.95 129.69 0 0 s5 3.3v s5_3.3v 6.77 6.85 11.03 7.2 5.87 5.84 avddtx 190.56 190.59 190. 73 191.49 11.52 11.51 avddrx 201.28 201.29 201.4 203.34 0 0 avddck_3.3v 4.69 4. 7 4.79 4.86 0 0 total s5 3.3v 403.3 403.43 407.95 406.89 17.39 17.35 other voltages cpu_pwr (1.05v) 0.06 0.14 1.55 4.24 0 0 v5_vref (5v) 0.19 0.68 0.56 2.53 0 0 total current (ma) 1799.9 1808.34 1830.11 1863.41 18.64 18.55 total power (w) 3.239 3.242 3.262 3.314 0.059 0.059 case temp (oc) 38.6 39.8 39.9 40.3 25.8 25.8
?2007- 2008 advanced micro devices, inc. package information sb600 databook proprietary page 85 10 package information 10.1 physical dimensions figure 10-1: sb600 23 mm x 23 mm 0.8 mm pitch 549-fcbga package outline* * note: this diagram does not show the ball at position a1, which onl y exists on asic a11. see t he product advisory titled sb600 ball-out change notice (an_ixp600aa1) for details. table 10-1: sb600 package physical dimensions ref. min(mm) nominal (mm) max. (mm) c 0.96 1.06 1.16 a** 2.18 2.33 2.48 a1 0.30 0.40 0.50 a2 0.84 0.87 0.90 b 0.40 0.50 0.60 d1 22.80 23.00 23.20 d2 - 6.37 - e1 22.80 23.00 23.20 e2 - 5.62 - f1 - 21.60 - f2 - 21.60 - e - 0.80 - ddd - - 0.15 ** note: dimension of ?a? subject to change according to actual measurement.
?2007- 2008 advanced micro devices, inc. package information sb600 databook proprietary page 86 10.2 pressure specification to avoid damages to the asic (die or solder ball join t cracks) caused by improper mechanical assembly of the cooling device, follow the recommendations below: ? it is recommended that the maximum pressure which is evenly applied across the contact area between the thermal management device and t he die does not exceed 40 psi. note that a contact pressure of 30-40 psi is adequate to secure the thermal management device and achieve the lowest thermal c ontact resistance with a temper ature drop across the thermal interface material of no more than 3c. also, the surface flatness of the metal spreader should be 0.001 inch/1 inch. ? pre-test the assembly fixture with a strain gauge to make sure that the flexing of the final assembled board and the pressure applying around the asic package will not exceed 600 micron strain under any circumstances. ? ensure that any distortion (bow or twist) of the board after smt and cooling device assembly is within industry guidelines (ipc/eia j-std-001). for measurement method, refer to the industry approved technique described in the m anual ipc-tm-650, section 2.4.22.
?2007- 2008 advanced micro devices, inc. thermal information sb600 databook proprietary page 87 11 thermal information this section describes some key thermal param eters of the sb600. for a detailed discussion on these parameters and other thermal design descr iptions including package level thermal data and analysis, please consult the thermal design and analysis guidelines for sb600. table 11-1: sb600 thermal limits parameter minimum nominal maximum unit note operating case temperature 0 ? 105 c 1 absolute rated junction temperature ? ? 125 c 2 storage temperature -40 ? 60 c ambient temperature 0 ? 45 c 3 thermal design power ? 4.0 ? w 4 notes: 1 - the maximum operating case temperature is the die geo metric top-center temperat ure measured through proper thermal contact to the back side of the die ba sed on the methodology given in the document thermal design and analysis guidelines for sb600 (chapter 11). this is the temperature at whic h the functionality of t he chip is qualified. 2 - the maximum absolute rated junction temperature is the junction temperature at which the device can operate without causing damage to the asic. this temperature can be measured via the integrated thermal diode described in the next section. 3 - the ambient temperature is defined as the temperature of the local intake air to the thermal management device. the maximum ambient temperature is dependent on the heat si nk's local ambient conditions as well as the chassis' external ambient, and the value given here is based on am d?s reference desktop heat sink solution for the sb600. refer to chapter 5 in the thermal design and analysis guidelines for sb600 for heatsink and thermal design guidelines. refer to chapter 6 of the above mentio ned document for details of ambient conditions. 4 - thermal design power (tdp) is defined as the highest power dissipated while running currently available worst case applications at nominal voltages. since the core power of modern asics using 65nm and smaller process technology can vary significantly, parts specifically screened for higher core power were used for tdp measurement. the tdp is intended only as a design reference, and the value given here is preliminary.
?2007- 2008 advanced micro devices, inc. testability sb600 databook proprietary page 88 12 testability 12.1 test control signals table 12-1 below shows the signals used for the in tegrated test controller of the sb600. table 12-1: signals for the test controller of the sb600 signal name ball ref. description 14m_osc a23 14.318mhz reference clock. test0 g9 test0 input. test1 e9 test1 input. test2 f9 test2 input. table 12-2 shows how test[2:0] are used to select the normal operation, asic debug, or test mode. table 12-2: test mode signals test2 test1 test0 test mode description 0 0 0 none normal operation 0 0 1 reserved reserved for asic debug 0 1 x test mode enabletest mode 1 x x reserved reserved for asic debug when test2 is low, a low on test1 will reset all test logic and allow test0 to choose between normal operation and the reserved debug mode. a high on test1 should be followed by a bit sequence on test0 to define the test mode into which the sb600 will enter. a new test mode can be entered when a new bit sequence is transmitted. in addition to resetti ng the test controller asynchronously with test1, a bit sequence can also be used to synchronously change the test mode. table 12-3 shows the legal bit sequences for test0. table 12-3: test0 bit sequence test0 bit sequence test mode 11111 look for first 0 to define a new test mode 00000 reserved 00001 alt pull high test 00010 pull outputs high 00011 pull outputs low 00100 pull outputs to z 00101 xor test mode figure 12-1 illustrates the data timing for the test signals with respect to the osc clock. note that once test1 is set to one, test0 needs to be asserted to one for at least 8 clocks before transmitting the test mode bit sequence. the rising of ?internal test mode ? in the diagram indicates the time when the sb600 enters into test mode.
?2007- 2008 advanced micro devices, inc. testability sb600 databook proprietary page 89 test0 test1 osc ( test0 = 1 ) > 8 osc clocks bit 4 bit 1 bit 2 bit 3 bit 0 internal test mode figure 12-1 test mode capturing sequence timing 12.2 xor chain test mode 12.2.1 brief descripti on of an xor chain a sample of a generic xor chain is shown in the figure below. xor start signal g f e d c b a figure 12-2: a generic xor chain pin a is assigned to the output direction, and pins b through f are assigned to the input direction. it can be seen that after all pins from b to f are assigned to logic 0 or 1, a logic change in any one of these pins will toggle the output pin a. the following is the truth table for the xor chain shown in figure 12-2. the xor start signal is assumed to be logic 1. table 12-4: truth table for an xor chain test vector number input pin g input pin f input pin e input pin d input pin c input pin b output pin a 1 0 0 0 0 0 0 1 2 1 0 0 0 0 0 0 3 1 1 0 0 0 0 1 4 1 1 1 0 0 0 0 5 1 1 1 1 0 0 1 6 1 1 1 1 1 0 0 7 1 1 1 1 1 1 1
?2007- 2008 advanced micro devices, inc. testability sb600 databook proprietary page 90 12.2.2 description of the sb600 xor chain during xor chain test mode, most of the chip pads on the sb600 are connected together using xor gates as shown in figure 12-3 . the first input of the chain is connected to a logic level high, and all pads are configured as inputs except for the last pad in the chain, which is configured as an output. ad6/roma12 is the start of the chain and frame# is the end of the chain. table 12-5 lists all pads that are on the sb600 xor chain, as well as and their order of connection. pads are chained together in the shown order, i.e., pad number 1 is the first pad on t he xor chain, pad number 2 the second, and so on. 1 pin 1 pin 2 pin 3 pin n xor out figure 12-3: on-chip xor chain connectivity table 12-5: list of pins on the sb600 xor chain and the order of connection xor # pin name pin # 1 ad6/roma12 aa6 2 ad31 ag1 3 ad27 ah1 4 ad8/roma9 aa7 5 ad23/romd7 ah3 6 gnt1# af2 7 inth#/gpio36 af3 8 ad25 ah2 9 ad28 ad2 10 ad29 ag2 11 intg#/gpio35 af4 12 ad7/roma11 ac5 13 intf#/gpio34 af1 14 ad21/romd5 aj3 15 ad12/roma5 ad4 16 irdy# ag5 17 ad10/roma7 ac7 18 ad15/roma2 ac9 19 req1# ae2 20 ad19/romd3 ah4 21 lock# af6 22 cbe2#/romwe# aj5 23 gnt4#/gpio73 ag4 24 req4#/gpio71 ah5 25 ad11/roma6 aj7 26 cpu_stp#/dpslp_3v# ah9 27 gnt0# ad11 28 clkrun# ag7 29 ad14/roma3 ae6 30 cbe3# ag3 31 devsel#/roma0 ah6 32 a_rst# ag10 xor # pin name pin # 33 ad13/roma4 ab11 34 gnt2# ah7 35 sata_act#/gpio67 ac12 36 serr# ac11 37 ad17/romd1 aj4 38 pcirst# aj9 39 req0# aj8 40 perr# ag8 41 cbe1#/roma1 af9 42 gnt3#/gpio72 ab12 43 req2# ag9 44 req3#/gpio70 ah8 45 lad1 ag25 46 lad3 ah25 47 serirq af23 48 ldrq0# aj24 49 lad2 ah24 50 kbrst# ag26 51 lad0 ag24 52 ga20in af26 53 ldrq1#/gnt5#/gpio68 ah26 54 lframe# af24 55 ide_d7/gpio22 aj27 56 ide_d14/gpio29 ad25 57 ide_d9/gpio24 ag27 58 ide_d10/gpio25 ag28 59 ide_d8/gpio23 ah27 60 ide_d1/gpio16 ad26 61 ide_d3/gpio18 af27 62 ide_d13/gpio28 ae28 63 ide_d6/gpio21 aj28 64 ide_d12/gpio27 af29
?2007- 2008 advanced micro devices, inc. testability sb600 databook proprietary page 91 xor # pin name pin # 65 ide_ior# ac29 66 ide_cs1# w28 67 ide_drq ac27 68 ide_d5/gpio20 ah28 69 ide_d11/gpio26 af28 70 ide_d4/gpio19 ag29 71 ide_d2/gpio17 ae29 72 ide_iow# ac28 73 ide_cs3# w27 74 ide_irq aa28 75 ide_dack# ab28 76 ide_a1 ab27 77 ide_a2 y28 78 ide_d0/gpio15 ad28 79 ide_d15/gpio30 ad29 80 ide_a0 aa29 81 ide_iordy ab29 82 stpclk#/ allow_ldtstp aa25 83 a20m#/sid aa26 84 slp#/ldt_stp# aa23 85 ferr# y27 86 ldt_rst#/ dprstp#/prochot# ac25 87 ddc1_scl/gpio9 d26 88 dprslpvr w23 89 bmreq#/req5#/gpio65 w22 90 rom_cs#/gpio1 a26 91 spkr/gpio2 b26 92 lpc_smi#/extevnt1# c25 93 dpslp_od#/gpio37 b24 94 ddc1_sda/gpio8 c26 95 shutdown#/gpio5/ smartvolt2 d23 96 lan_rst#/gpio13 c23 97 sda0/gpoc1# b28 98 sata_is0#/gpio10 c28 99 ssmuxsel/ sata_is3#/gpio0 a27 100 scl0/gpoc0# c27 101 wd_pwrgd/gpio7 a23 102 smartvolt/ sata_is2#/gpio4 b27 103 ghi#/sata_is1#/gpio6 b29 104 rtc_irq#/gpio69 f5 105 sus_stat# b3 106 usb_oc8#/az_dock _rst#/gpm8# c5 107 lpc_pme#/gevent3# d7 108 usb_oc5#/ddr3_rst# /gpm5# b6 109 usb_oc9#/slp_s2/ gpm9# c6 xor # pin name pin # 110 blink/gpm6# c2 111 usb_oc2#/gpm2# c7 112 pwr_btn# e3 113 pci_pme#/gevent4# a3 114 usb_oc6#/gevent6# b4 115 usb_oc0#/gpm0# a8 116 spi_cs#/gpio32 g6 117 spi_clk/gpio47 g3 118 spi_di/gpio12 j3 119 spi_do/gpio11 j6 120 ri#/extevnt0# b2 121 usb_oc7#/gevent7# c4 122 usb_oc1#/gpm1# b8 123 spi_hold#/gpio31 g2 124 usb_oc4#/gpm4# a6 125 rom_rst#/gpio14 g5 126 smbalert#/thrm trip#/gevent2# g7 127 sys_reset#/gpm7# f4 128 s3_state/gevent5# d9 129 sda1/gpoc3# f3 130 scl1/gpoc2# c3 131 llb#/gpio66 a4 132 wake#/gevent8# e7 133 ac_rst#/gpio45 l5 134 acz_sdin0/gpio42 l4 135 acz_sdin2/gpio44 j4 136 acz_sdin1/gpio43 j2 137 az_rst# k3 138 az_sdin3/gpio46 k2 139 tempin1/gpio62 p8 140 tempin0/gpio61 p7 141 vin6/gpio59 m7 142 vin1/gpio54 l7 143 vin2/gpio55 m8 144 vin4/gpio57 m6 145 vin0/gpio53 v5 146 vin5/gpio58 p4 147 tempin2/gpio63 t8 148 vin7/gpio60 v7 149 vin3/gpio56 v6 150 tempin3/talert#/ gpio64 t7 151 az_sync l3 152 az_bitclk n2 153 az_sdout m2 154 fanin0/gpio50 n3 155 fanin1/gpio51 p2 156 fanin2/gpio52 w4 157 fanout1/gpio48 t3 158 fanout2/gpio49 v4 159 ac_sdout/gpio39 l2 160 ac_bitclk/gpio38 l1
?2007- 2008 advanced micro devices, inc. testability sb600 databook proprietary page 92 xor # pin name pin # 161 ac_sync/gpio40 m3 162 spdif_out/pciclk7/ gpio41 t1 163 pciclk6 v1 164 pciclk0 u2 165 pciclk5 u3 166 pciclk2 u1 167 pciclk1 t2 168 pciclk4 w3 169 pciclk3 v2 170 ad1/roma17 y1 171 ad0/roma18 w7 172 ad4/roma14 aa5 173 ad3/roma15 w5 174 stop# y2 175 trdy#/romoe# aa1 xor # pin name pin # 176 ad20/romd4 ab2 177 ad16/romd0 aa3 178 ad18/romd2 ab1 179 inte#/gpio33 ad3 180 ad2/roma16 w8 181 ad22/romd6 ab3 182 ad9/roma8 ac3 183 ad24 ac1 184 ad5/roma13 y3 185 cbe0#/roma10 ab9 186 par/roma19 af7 187 ad30 ad1 188 ad26 ac2 189 frame# aa2 12.2.2.1 unused pins the pins that are part of the xor chain (see table 12-5 ) but are not used for testing must be pulled up or down before the xor chain is activated. no pins in the xor chain should be left floating. all digital or analog pins not included in table 12-5 are not part of the xor chain and can be left floating during an xor test. that includes the output of the xor chain, fanout0/gpio3, and other pads shown in table 12-6 below. table 12-6: pins excluded from the xor chain pin name pin # description rsmrst# e2 used for capturing straps pwr_good b5 used for capturing straps slp_s5# a5 in s5 power well. no test support. slp_s3# f7 in s5 power well. no test support. cpu_pg/ldt_pg ac26 no test support ignne#/sic aa22 no test support smi# aa24 no test support nmi/lint1 w24 no test support intr/lint0 w26 no test support init# w25 no test support usb_oc3#/gpm3# b7 no test support test0 g9 test controller data input test1 e9 test controller mode test2 f9 reserved test input 14m_osc b23 test control clock rtcclk d3 no test support fanout0/gpio3 m4 out put of the xor chain
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 93 appendix a: pin listing table 12-7: sb600 pin list sorted by interface ball no. signal name cpu interface ac26 cpu_pg/ldt_pg w26 intr/lint0 w24 nmi/lint1 w25 init# aa24 smi# aa23 slp#/ldt_stp# aa22 ignne#/sic aa26 a20m#/sid y27 ferr# aa25 stpclk#/allow_ldtstp w23 dprslpvr aa27 cpu_pwr ac25 ldt_rst#/dprstp#/pro chot# lpc interface ag24 lad0 ag25 lad1 ah24 lad2 ah25 lad3 af24 lframe# aj24 ldrq0# ah26 ldrq1#/gnt5#/gpio68 c25 lpc_smi#/extevnt1# af23 serirq af26 ga20in ag26 kbrst# pci express interface j24 pcie_rclkp j25 pcie_rclkn p29 pcie_tx0p p28 pcie_tx0n m29 pcie_tx1p m28 pcie_tx1n ball no. signal name k29 pcie_tx2p k28 pcie_tx2n h29 pcie_tx3p h28 pcie_tx3n t25 pcie_rx0p t26 pcie_rx0n t22 pcie_rx1p t23 pcie_rx1n m25 pcie_rx2p m26 pcie_rx2n m22 pcie_rx3p m23 pcie_rx3n e29 pcie_calrp e28 pcie_calrn e27 pcie_cali pci 33 interface u2 pciclk0 t2 pciclk1 u1 pciclk2 v2 pciclk3 w3 pciclk4 u3 pciclk5 v1 pciclk6 t1 spdif_out/pciclk7/gpi o41 aj9 pcirst# ad3 inte#/gpio33 af1 intf#/gpio34 af4 intg#/gpio35 af3 inth#/gpio36 w7 ad0/roma18 y1 ad1/roma17 w8 ad2/roma16 w5 ad3/roma15 aa5 ad4/roma14 ball no. signal name y3 ad5/roma13 aa6 ad6/roma12 ac5 ad7/roma11 aa7 ad8/roma9 ac3 ad9/roma8 ac7 ad10/roma7 aj7 ad11/roma6 ad4 ad12/roma5 ab11 ad13/roma4 ae6 ad14/roma3 ac9 ad15/roma2 aa3 ad16/romd0 aj4 ad17/romd1 ab1 ad18/romd2 ah4 ad19/romd3 ab2 ad20/romd4 aj3 ad21/romd5 ab3 ad22/romd6 ah3 ad23/romd7 ac1 ad24 ah2 ad25 ac2 ad26 ah1 ad27 ad2 ad28 ag2 ad29 ad1 ad30 ag1 ad31 ab9 cbe0#/roma10 af9 cbe1#/roma1 aj5 cbe2#/romwe# ag3 cbe3# aa2 frame# ah6 devsel#/roma0 ag5 irdy#
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 94 ball no. signal name aa1 trdy#/romoe# af7 par/roma19 y2 stop# ag8 perr# ac11 serr# af6 lock# aj8 req0# ae2 req1# ag9 req2# ah8 req3#/gpio70 ah5 req4#/gpio71 w22 bmreq#/req5#/gpio65 ad11 gnt0# af2 gnt1# ah7 gnt2# ab12 gnt3#/gpio72 ag4 gnt4#/gpio73 ah26 ldrq1#/gnt5#/gpio68 ag7 clkrun# usb interface h12 usb_hsdp9+ g12 usb_hsdm9- e12 usb_hsdp8+ d12 usb_hsdm8- e14 usb_hsdp7+ d14 usb_hsdm7- g14 usb_hsdp6+ h14 usb_hsdm6- d16 usb_hsdp5+ e16 usb_hsdm5- d18 usb_hsdp4+ e18 usb_hsdm4- g16 usb_hsdp3+ h16 usb_hsdm3- g18 usb_hsdp2+ h18 usb_hsdm2- d19 usb_hsdp1+ ball no. signal name e19 usb_hsdm1- g19 usb_hsdp0+ h19 usb_hsdm0- a17 usbclk a14 usb_rcomp a11 usb_atest1 a10 usb_atest0 ata66/100/133 ab29 ide_iordy aa28 ide_irq aa29 ide_a0 ab27 ide_a1 y28 ide_a2 ab28 ide_dack# ac27 ide_drq ac29 ide_ior# ac28 ide_iow# w28 ide_cs1# w27 ide_cs3# ad28 ide_d0/gpio15 ad26 ide_d1/gpio16 ae29 ide_d2/gpio17 af27 ide_d3/gpio18 ag29 ide_d4/gpio19 ah28 ide_d5/gpio20 aj28 ide_d6/gpio21 aj27 ide_d7/gpio22 ah27 ide_d8/gpio23 ag27 ide_d9/gpio24 ag28 ide_d10/gpio25 af28 ide_d11/gpio26 af29 ide_d12/gpio27 ae28 ide_d13/gpio28 ad25 ide_d14/gpio29 ad29 ide_d15/gpio30 serial ata ah21 sata_tx0+ ball no. signal name aj21 sata_tx0- ah20 sata_rx0- aj20 sata_rx0+ ah18 sata_tx1+ aj18 sata_tx1- ah17 sata_rx1- aj17 sata_rx1+ ah13 sata_tx2+ ah14 sata_tx2- ah16 sata_rx2- aj16 sata_rx2+ aj11 sata_tx3+ ah11 sata_tx3- ah12 sata_rx3- aj13 sata_rx3+ af12 sata_cal ad16 sata_x1 ad18 sata_x2 ac12 sata_act#/gpio67 c28 sata_is0#/gpio10 b29 ghi#/sata_is1#/gpio6 b27 smartvolt/sata_is2#/g pio4 a27 ssmuxsel/sata_is3#/gp io0 ac ?97 interface l1 ac_bitclk/gpio38 l2 ac_sdout/gpio39 l4 acz_sdin0/gpio42 j2 acz_sdin1/gpio43 j4 acz_sdin2/gpio44 m3 ac_sync/gpio40 l5 ac_rst#/gpio45 t1 spdif_out/pciclk7/gpi o41 hd interface n2 az_bitclk m2 az_sdout l3 az_sync
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 95 ball no. signal name k3 az_rst# k2 az_sdin3/gpio46 real time clock d2 x1 c1 x2 d1 rtc_gnd e1 vbat f5 rtc_irq#/gpio69 d3 rtcclk hardware monitor m4 fanout0/gpio3 t3 fanout1/gpio48 v4 fanout2/gpio49 n3 fanin0/gpio50 p2 fanin1/gpio51 w4 fanin2/gpio52 p5 temp_comm p7 tempin0/gpio61 p8 tempin1/gpio62 t8 tempin2/gpio63 t7 tempin3/talert#/gpio6 4 v5 vin0/gpio53 l7 vin1/gpio54 m8 vin2/gpio55 v6 vin3/gpio56 m6 vin4/gpio57 p4 vin5/gpio58 m7 vin6/gpio59 v7 vin7/gpio60 n1 avdd m1 avss spi rom interface j3 spi_di/gpio12 j6 spi_do/gpio11 g3 spi_clk/gpio47 g2 spi_hold#/gpio31 g6 spi_cs#/gpio32 ball no. signal name nb / power mgmt b24 dpslp_od#/gpio37 ah9 cpu_stp#/dpslp_3v# f7 slp_s3# a5 slp_s5# c6 usb_oc9#/slp_s2/gpm9 # e3 pwr_btn# b5 pwr_good b3 sus_stat# g9 test0 e9 test1 f9 test2 general events b2 ri#/extevnt0# c25 lpc_smi#/extevnt1# g7 smbalert#/thrmtrip#/ gevent2# d7 lpc_pme#/gevent3# a3 pci_pme#/gevent4# d9 s3_state/gevent5# b4 usb_oc6#/gevent6# c4 usb_oc7#/gevent7# e7 wake#/gevent8# a8 usb_oc0#/gpm0# b8 usb_oc1#/gpm1# c7 usb_oc2#/gpm2# c8 usb_oc3#/gpm3# a6 usb_oc4#/gpm4# b6 usb_oc5#/ddr3_rst#/g pm5# c2 blink/gpm6# f4 sys_reset#/gpm7# c5 usb_oc8#/az_dock_rs t#/gpm8# c6 usb_oc9#/slp_s2/gpm9 # sm bus/ gpoc c27 scl0/gpoc0# ball no. signal name b28 sda0/gpoc1# c3 scl1/gpoc2# f3 sda1/gpoc3# general purpose i/o a27 ssmuxsel/sata_is3#/gp io0 a26 rom_cs#/gpio1 b26 spkr/gpio2 m4 fanout0/gpio3 b27 smartvolt/sata_is2#/g pio4 d23 shutdown#/gpio5/sma rtvolt2 b29 ghi#/sata_is1#/gpio6 a23 wd_pwrgd/gpio7 c26 ddc1_sda/gpio8 d26 ddc1_scl/gpio9 c28 sata_is0#/gpio10 j6 spi_do/gpio11 j3 spi_di/gpio12 c23 lan_rst#/gpio13 g5 rom_rst#/gpio14 ad28 ide_d0/gpio15 ad26 ide_d1/gpio16 ae29 ide_d2/gpio17 af27 ide_d3/gpio18 ag29 ide_d4/gpio19 ah28 ide_d5/gpio20 aj28 ide_d6/gpio21 aj27 ide_d7/gpio22 ah27 ide_d8/gpio23 ag27 ide_d9/gpio24 ag28 ide_d10/gpio25 af28 ide_d11/gpio26 af29 ide_d12/gpio27 ae28 ide_d13/gpio28 ad25 ide_d14/gpio29 ad29 ide_d15/gpio30 g2 spi_hold#/gpio31
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 96 ball no. signal name g6 spi_cs#/gpio32 ad3 inte#/gpio33 af1 intf#/gpio34 af4 intg#/gpio35 af3 inth#/gpio36 b24 dpslp_od#/gpio37 l1 ac_bitclk/gpio38 l2 ac_sdout/gpio39 m3 ac_sync/gpio40 t1 spdif_out/pciclk7/gpi o41 l4 acz_sdin0/gpio42 j2 acz_sdin1/gpio43 j4 acz_sdin2/gpio44 l5 ac_rst#/gpio45 k2 az_sdin3/gpio46 g3 spi_clk/gpio47 t3 fanout1/gpio48 v4 fanout2/gpio49 n3 fanin0/gpio50 p2 fanin1/gpio51 w4 fanin2/gpio52 v5 vin0/gpio53 l7 vin1/gpio54 m8 vin2/gpio55 v6 vin3/gpio56 m6 vin4/gpio57 p4 vin5/gpio58 m7 vin6/gpio59 v7 vin7/gpio60 p7 tempin0/gpio61 p8 tempin1/gpio62 t8 tempin2/gpio63 t7 tempin3/talert#/gpio6 4 w22 bmreq#/req5#/gpio65 a4 llb#/gpio66 ac12 sata_act#/gpio67 ball no. signal name ah26 ldrq1#/gnt5#/gpio68 f5 rtc_irq#/gpio69 ah8 req3#/gpio70 ab12 gnt3#/gpio72 ah5 req4#/gpio71 ag4 gnt4#/gpio73 reset / clocks ag10 a_rst# e2 rsmrst# b23 14m_osc no connects (empty balls) e23 nc1 ac21 nc2 ad7 nc3 ae7 nc4 aa4 nc5 t4 nc6 d4 nc7 ab19 nc8 special power / gnd a24 avddck_3.3v a22 avddck_1.2v b22 avssck ae11 v5_vref usb analog pwr b9 avddtx_0 b11 avddtx_1 b13 avddtx_2 b16 avddtx_3 b18 avddtx_4 a9 avddrx_0 b10 avddrx_1 b12 avddrx_2 b14 avddrx_3 b17 avddrx_4 a12 avddc a13 avssc ball no. signal name usb analog gnd a16 avss_usb_1 c9 avss_usb_2 c10 avss_usb_3 c11 avss_usb_4 c12 avss_usb_5 c13 avss_usb_6 c14 avss_usb_7 c16 avss_usb_8 c17 avss_usb_9 c18 avss_usb_10 c19 avss_usb_11 c20 avss_usb_12 d11 avss_usb_13 d21 avss_usb_14 e11 avss_usb_15 e21 avss_usb_16 f11 avss_usb_17 f12 avss_usb_18 f14 avss_usb_19 f16 avss_usb_20 f18 avss_usb_21 f19 avss_usb_22 f21 avss_usb_23 g11 avss_usb_24 g21 avss_usb_25 h11 avss_usb_26 h21 avss_usb_27 j11 avss_usb_28 j12 avss_usb_29 j14 avss_usb_30 j16 avss_usb_31 j18 avss_usb_32 j19 avss_usb_33 pci express analog power u29 pcie_pvdd f27 pcie_vddr_1
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 97 ball no. signal name f28 pcie_vddr_2 f29 pcie_vddr_3 g26 pcie_vddr_4 g27 pcie_vddr_5 g28 pcie_vddr_6 g29 pcie_vddr_7 j27 pcie_vddr_8 j29 pcie_vddr_9 l25 pcie_vddr_10 l26 pcie_vddr_11 l29 pcie_vddr_12 n29 pcie_vddr_13 pci-e analog ground u28 pcie_pvss d27 pcie_vss_1 d28 pcie_vss_2 d29 pcie_vss_3 f26 pcie_vss_4 g23 pcie_vss_5 g24 pcie_vss_6 g25 pcie_vss_7 h27 pcie_vss_8 j23 pcie_vss_9 j26 pcie_vss_10 j28 pcie_vss_11 k27 pcie_vss_12 l22 pcie_vss_13 l23 pcie_vss_14 l24 pcie_vss_15 l27 pcie_vss_16 l28 pcie_vss_17 m21 pcie_vss_18 m24 pcie_vss_19 m27 pcie_vss_20 n27 pcie_vss_21 n28 pcie_vss_22 p22 pcie_vss_23 ball no. signal name p23 pcie_vss_24 p24 pcie_vss_25 p25 pcie_vss_26 p26 pcie_vss_27 p27 pcie_vss_28 t21 pcie_vss_29 t24 pcie_vss_30 t27 pcie_vss_31 t28 pcie_vss_32 t29 pcie_vss_33 u27 pcie_vss_34 v22 pcie_vss_35 v23 pcie_vss_36 v24 pcie_vss_37 v25 pcie_vss_38 v26 pcie_vss_39 v27 pcie_vss_40 v28 pcie_vss_41 v29 pcie_vss_42 serial ata analog pwr ae14 avdd_sata_1 ae16 avdd_sata_2 ae18 avdd_sata_3 ae19 avdd_sata_4 af19 avdd_sata_5 af21 avdd_sata_6 ag22 avdd_sata_7 ag23 avdd_sata_8 ah22 avdd_sata_9 ah23 avdd_sata_10 aj12 avdd_sata_11 aj14 avdd_sata_12 aj19 avdd_sata_13 aj22 avdd_sata_14 aj23 avdd_sata_15 ac16 xtlvdd_sata ad14 pllvdd_sata_1 ball no. signal name aj10 pllvdd_sata_2 serial ata analog ground ab14 avss_sata_1 ab16 avss_sata_2 ab18 avss_sata_3 ac14 avss_sata_4 ac18 avss_sata_5 ac19 avss_sata_6 ad12 avss_sata_7 ad19 avss_sata_8 ad21 avss_sata_9 ae12 avss_sata_10 ae21 avss_sata_11 af11 avss_sata_12 af14 avss_sata_13 af16 avss_sata_14 af18 avss_sata_15 ag11 avss_sata_16 ag12 avss_sata_17 ag13 avss_sata_18 ag14 avss_sata_19 ag16 avss_sata_20 ag17 avss_sata_21 ag18 avss_sata_22 ag19 avss_sata_23 ag20 avss_sata_24 ag21 avss_sata_25 ah10 avss_sata_26 ah19 avss_sata_27 core pwr m13 vdd_1 m17 vdd_2 n12 vdd_3 n15 vdd_4 n18 vdd_5 r13 vdd_6 r17 vdd_7
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 98 ball no. signal name u12 vdd_8 u15 vdd_9 u18 vdd_10 v13 vdd_11 v17 vdd_12 3.3v i/o pwr a25 vddq_1 a28 vddq_2 c29 vddq_3 d24 vddq_4 l9 vddq_5 l21 vddq_6 m5 vddq_7 p3 vddq_8 p9 vddq_9 t5 vddq_10 v9 vddq_11 w2 vddq_12 w6 vddq_13 w21 vddq_14 w29 vddq_15 aa12 vddq_16 aa16 vddq_17 aa19 vddq_18 ac4 vddq_19 ac23 vddq_20 ad27 vddq_21 ae1 vddq_22 ae9 vddq_23 ae23 vddq_24 ah29 vddq_25 aj2 vddq_26 aj6 vddq_27 aj26 vddq_28 3.3v standby pwr a2 s5_3.3v_1 a7 s5_3.3v_2 ball no. signal name f1 s5_3.3v_3 j5 s5_3.3v_4 j7 s5_3.3v_5 k1 s5_3.3v_6 1.2v standby pwr g4 s5_1.2v_1 h1 s5_1.2v_2 h2 s5_1.2v_3 h3 s5_1.2v_4 usb phy digital power a18 usb_phy_1.2v_1 a19 usb_phy_1.2v_2 b19 usb_phy_1.2v_3 b20 usb_phy_1.2v_4 b21 usb_phy_1.2v_5 digital ground a1 asic a11: vss_1 asic a12 and after: no ball at the position a20 vss_2 a21 vss_3 a29 vss_4 b1 vss_5 b7 vss_6 b25 vss_7 c21 vss_8 c22 vss_9 c24 vss_10 d6 vss_11 e24 vss_12 f2 vss_13 f23 vss_14 g1 vss_15 j1 vss_16 j8 vss_17 l6 vss_18 l8 vss_19 m9 vss_20 ball no. signal name m12 vss_21 m15 vss_22 m18 vss_23 n13 vss_24 n17 vss_25 p1 vss_26 p6 vss_27 p21 vss_28 r12 vss_29 r15 vss_30 r18 vss_31 t6 vss_32 t9 vss_33 u13 vss_34 u17 vss_35 v3 vss_36 v8 vss_37 v12 vss_38 v15 vss_39 v18 vss_40 v21 vss_41 w1 vss_42 w9 vss_43 y29 vss_44 aa11 vss_45 aa14 vss_46 aa18 vss_47 ac6 vss_48 ac24 vss_49 ad9 vss_50 ad23 vss_51 ae3 vss_52 ae27 vss_53 ag6 vss_54 aj1 vss_55 aj25 vss_56 aj29 vss_57
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 99 table 12-8: sb600 pin list sorted by ball reference ball no. signal name a1 asic a11: vss_1 asic a12 and after: no ball at the position a10 usb_atest0 a11 usb_atest1 a12 avddc a13 avssc a14 usb_rcomp a16 avss_usb_1 a17 usbclk a18 usb_phy_1.2v_1 a19 usb_phy_1.2v_2 a2 s5_3.3v_1 a20 vss_2 a21 vss_3 a22 avddck_1.2v a23 wd_pwrgd/gpio7 a24 avddck_3.3v a25 vddq_1 a26 rom_cs#/gpio1 a27 ssmuxsel/sata_is3#/gp io0 a28 vddq_2 a29 vss_4 a3 pci_pme#/gevent4# a4 llb#/gpio66 a5 slp_s5# a6 usb_oc4#/gpm4# a7 s5_3.3v_2 a8 usb_oc0#/gpm0# a9 avddrx_0 aa1 trdy#/romoe# aa11 vss_45 aa12 vddq_16 aa14 vss_46 aa16 vddq_17 ball no. signal name aa18 vss_47 aa19 vddq_18 aa2 frame# aa22 ignne#/sic aa23 slp#/ldt_stp# aa24 smi# aa25 stpclk#/allow_ldtstp aa26 a20m#/sid aa27 cpu_pwr aa28 ide_irq aa29 ide_a0 aa3 ad16/romd0 aa4 nc5 aa5 ad4/roma14 aa6 ad6/roma12 aa7 ad8/roma9 ab1 ad18/romd2 ab11 ad13/roma4 ab12 gnt3#/gpio72 ab14 avss_sata_1 ab16 avss_sata_2 ab18 avss_sata_3 ab19 nc8 ab2 ad20/romd4 ab27 ide_a1 ab28 ide_dack# ab29 ide_iordy ab3 ad22/romd6 ab9 cbe0#/roma10 ac1 ad24 ac11 serr# ac12 sata_act#/gpio67 ac14 avss_sata_4 ac16 xtlvdd_sata ac18 avss_sata_5 ball no. signal name ac19 avss_sata_6 ac2 ad26 ac21 nc2 ac23 vddq_20 ac24 vss_49 ac25 ldt_rst#/dprstp#/pro chot# ac26 cpu_pg/ldt_pg ac27 ide_drq ac28 ide_iow# ac29 ide_ior# ac3 ad9/roma8 ac4 vddq_19 ac5 ad7/roma11 ac6 vss_48 ac7 ad10/roma7 ac9 ad15/roma2 ad1 ad30 ad11 gnt0# ad12 avss_sata_7 ad14 pllvdd_sata_1 ad16 sata_x1 ad18 sata_x2 ad19 avss_sata_8 ad2 ad28 ad21 avss_sata_9 ad23 vss_51 ad25 ide_d14/gpio29 ad26 ide_d1/gpio16 ad27 vddq_21 ad28 ide_d0/gpio15 ad29 ide_d15/gpio30 ad3 inte#/gpio33 ad4 ad12/roma5 ad7 nc3 ad9 vss_50
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 100 ball no. signal name ae1 vddq_22 ae11 v5_vref ae12 avss_sata_10 ae14 avdd_sata_1 ae16 avdd_sata_2 ae18 avdd_sata_3 ae19 avdd_sata_4 ae2 req1# ae21 avss_sata_11 ae23 vddq_24 ae27 vss_53 ae28 ide_d13/gpio28 ae29 ide_d2/gpio17 ae3 vss_52 ae6 ad14/roma3 ae7 nc4 ae9 vddq_23 af1 intf#/gpio34 af11 avss_sata_12 af12 sata_cal af14 avss_sata_13 af16 avss_sata_14 af18 avss_sata_15 af19 avdd_sata_5 af2 gnt1# af21 avdd_sata_6 af23 serirq af24 lframe# af26 ga20in af27 ide_d3/gpio18 af28 ide_d11/gpio26 af29 ide_d12/gpio27 af3 inth#/gpio36 af4 intg#/gpio35 af6 lock# af7 par/roma19 af9 cbe1#/roma1 ball no. signal name ag1 ad31 ag10 a_rst# ag11 avss_sata_16 ag12 avss_sata_17 ag13 avss_sata_18 ag14 avss_sata_19 ag16 avss_sata_20 ag17 avss_sata_21 ag18 avss_sata_22 ag19 avss_sata_23 ag2 ad29 ag20 avss_sata_24 ag21 avss_sata_25 ag22 avdd_sata_7 ag23 avdd_sata_8 ag24 lad0 ag25 lad1 ag26 kbrst# ag27 ide_d9/gpio24 ag28 ide_d10/gpio25 ag29 ide_d4/gpio19 ag3 cbe3# ag4 gnt4#/gpio73 ag5 irdy# ag6 vss_54 ag7 clkrun# ag8 perr# ag9 req2# ah1 ad27 ah10 avss_sata_26 ah11 sata_tx3- ah12 sata_rx3- ah13 sata_tx2+ ah14 sata_tx2- ah16 sata_rx2- ah17 sata_rx1- ah18 sata_tx1+ ball no. signal name ah19 avss_sata_27 ah2 ad25 ah20 sata_rx0- ah21 sata_tx0+ ah22 avdd_sata_9 ah23 avdd_sata_10 ah24 lad2 ah25 lad3 ah26 ldrq1#/gnt5#/gpio68 ah27 ide_d8/gpio23 ah28 ide_d5/gpio20 ah29 vddq_25 ah3 ad23/romd7 ah4 ad19/romd3 ah5 req4#/gpio71 ah6 devsel#/roma0 ah7 gnt2# ah8 req3#/gpio70 ah9 cpu_stp#/dpslp_3v# aj1 vss_55 aj10 pllvdd_sata_2 aj11 sata_tx3+ aj12 avdd_sata_11 aj13 sata_rx3+ aj14 avdd_sata_12 aj16 sata_rx2+ aj17 sata_rx1+ aj18 sata_tx1- aj19 avdd_sata_13 aj2 vddq_26 aj20 sata_rx0+ aj21 sata_tx0- aj22 avdd_sata_14 aj23 avdd_sata_15 aj24 ldrq0# aj25 vss_56 aj26 vddq_28
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 101 ball no. signal name aj27 ide_d7/gpio22 aj28 ide_d6/gpio21 aj29 vss_57 aj3 ad21/romd5 aj4 ad17/romd1 aj5 cbe2#/romwe# aj6 vddq_27 aj7 ad11/roma6 aj8 req0# aj9 pcirst# b1 vss_5 b10 avddrx_1 b11 avddtx_1 b12 avddrx_2 b13 avddtx_2 b14 avddrx_3 b16 avddtx_3 b17 avddrx_4 b18 avddtx_4 b19 usb_phy_1.2v_3 b2 ri#/extevnt0# b20 usb_phy_1.2v_4 b21 usb_phy_1.2v_5 b22 avssck b23 14m_osc b24 dpslp_od#/gpio37 b24 dpslp_od#/gpio37 b25 vss_7 b26 spkr/gpio2 b27 smartvolt/sata_is2#/g pio4 b28 sda0/gpoc1# b29 ghi#/sata_is1#/gpio6 b3 sus_stat# b4 usb_oc6#/gevent6# b5 pwr_good b6 usb_oc5#/ddr3_rst#/g pm5# ball no. signal name b7 vss_6 b8 usb_oc1#/gpm1# b9 avddtx_0 c1 x2 c10 avss_usb_3 c11 avss_usb_4 c12 avss_usb_5 c13 avss_usb_6 c14 avss_usb_7 c16 avss_usb_8 c17 avss_usb_9 c18 avss_usb_10 c19 avss_usb_11 c2 blink/gpm6# c20 avss_usb_12 c21 vss_8 c22 vss_9 c23 lan_rst#/gpio13 c24 vss_10 c25 lpc_smi#/extevnt1# c26 ddc1_sda/gpio8 c27 scl0/gpoc0# c28 sata_is0#/gpio10 c29 vddq_3 c3 scl1/gpoc2# c4 usb_oc7#/gevent7# c5 usb_oc8#/az_dock_rs t#/gpm8# c6 usb_oc9#/slp_s2/ gpm9# c7 usb_oc2#/gpm2# c8 usb_oc3#/gpm3# c9 avss_usb_2 d1 rtc_gnd d11 avss_usb_13 d12 usb_hsdm8- d14 usb_hsdm7- d16 usb_hsdp5+ ball no. signal name d18 usb_hsdp4+ d19 usb_hsdp1+ d2 x1 d21 avss_usb_14 d23 shutdown#/gpio5/sma rtvolt2 d24 vddq_4 d26 ddc1_scl/gpio9 d27 pcie_vss_1 d28 pcie_vss_2 d29 pcie_vss_3 d3 rtcclk d4 nc7 d6 vss_11 d7 lpc_pme#/gevent3# d9 s3_state/gevent5# e1 vbat e11 avss_usb_15 e12 usb_hsdp8+ e14 usb_hsdp7+ e16 usb_hsdm5- e18 usb_hsdm4- e19 usb_hsdm1- e2 rsmrst# e21 avss_usb_16 e23 nc1 e24 vss_12 e27 pcie_cali e28 pcie_calrn e29 pcie_calrp e3 pwr_btn# e7 wake#/gevent8# e9 test1 f1 s5_3.3v_3 f11 avss_usb_17 f12 avss_usb_18 f14 avss_usb_19 f16 avss_usb_20
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 102 ball no. signal name f18 avss_usb_21 f19 avss_usb_22 f2 vss_13 f21 avss_usb_23 f23 vss_14 f26 pcie_vss_4 f27 pcie_vddr_1 f28 pcie_vddr_2 f29 pcie_vddr_3 f3 sda1/gpoc3# f4 sys_reset#/gpm7# f5 rtc_irq#/gpio69 f7 slp_s3# f9 test2 g1 vss_15 g11 avss_usb_24 g12 usb_hsdm9- g14 usb_hsdp6+ g16 usb_hsdp3+ g18 usb_hsdp2+ g19 usb_hsdp0+ g2 spi_hold#/gpio31 g21 avss_usb_25 g23 pcie_vss_5 g24 pcie_vss_6 g25 pcie_vss_7 g26 pcie_vddr_4 g27 pcie_vddr_5 g28 pcie_vddr_6 g29 pcie_vddr_7 g3 spi_clk/gpio47 g4 s5_1.2v_1 g5 rom_rst#/gpio14 g6 spi_cs#/gpio32 g7 smbalert#/thrmtrip#/ gevent2# g9 test0 h1 s5_1.2v_2 ball no. signal name h11 avss_usb_26 h12 usb_hsdp9+ h14 usb_hsdm6- h16 usb_hsdm3- h18 usb_hsdm2- h19 usb_hsdm0- h2 s5_1.2v_3 h21 avss_usb_27 h27 pcie_vss_8 h28 pcie_tx3n h29 pcie_tx3p h3 s5_1.2v_4 j1 vss_16 j11 avss_usb_28 j12 avss_usb_29 j14 avss_usb_30 j16 avss_usb_31 j18 avss_usb_32 j19 avss_usb_33 j2 acz_sdin1/gpio43 j23 pcie_vss_9 j24 pcie_rclkp j25 pcie_rclkn j26 pcie_vss_10 j27 pcie_vddr_8 j28 pcie_vss_11 j29 pcie_vddr_9 j3 spi_di/gpio12 j4 acz_sdin2/gpio44 j5 s5_3.3v_4 j6 spi_do/gpio11 j6 spi_do/gpio11 j7 s5_3.3v_5 j8 vss_17 k1 s5_3.3v_6 k2 az_sdin3/gpio46 k27 pcie_vss_12 ball no. signal name k28 pcie_tx2n k29 pcie_tx2p k3 az_rst# l1 ac_bitclk/gpio38 l2 ac_sdout/gpio39 l21 vddq_6 l22 pcie_vss_13 l23 pcie_vss_14 l24 pcie_vss_15 l25 pcie_vddr_10 l26 pcie_vddr_11 l27 pcie_vss_16 l28 pcie_vss_17 l29 pcie_vddr_12 l3 az_sync l4 acz_sdin0/gpio42 l5 ac_rst#/gpio45 l6 vss_18 l7 vin1/gpio54 l8 vss_19 l9 vddq_5 m1 avss m12 vss_21 m13 vdd_1 m15 vss_22 m17 vdd_2 m18 vss_23 m2 az_sdout m21 pcie_vss_18 m22 pcie_rx3p m23 pcie_rx3n m24 pcie_vss_19 m25 pcie_rx2p m26 pcie_rx2n m27 pcie_vss_20 m28 pcie_tx1n m29 pcie_tx1p
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 103 ball no. signal name m3 ac_sync/gpio40 m4 fanout0/gpio3 m5 vddq_7 m6 vin4/gpio57 m7 vin6/gpio59 m8 vin2/gpio55 m9 vss_20 n1 avdd n12 vdd_3 n13 vss_24 n15 vdd_4 n17 vss_25 n18 vdd_5 n2 az_bitclk n27 pcie_vss_21 n28 pcie_vss_22 n29 pcie_vddr_13 n3 fanin0/gpio50 p1 vss_26 p2 fanin1/gpio51 p21 vss_28 p22 pcie_vss_23 p23 pcie_vss_24 p24 pcie_vss_25 p25 pcie_vss_26 p26 pcie_vss_27 p27 pcie_vss_28 p28 pcie_tx0n p29 pcie_tx0p p3 vddq_8 p4 vin5/gpio58 p5 temp_comm p6 vss_27 p7 tempin0/gpio61 p8 tempin1/gpio62 p9 vddq_9 r12 vss_29 ball no. signal name r13 vdd_6 r15 vss_30 r17 vdd_7 r18 vss_31 t1 spdif_out/pciclk7/ gpio41 t2 pciclk1 t21 pcie_vss_29 t22 pcie_rx1p t23 pcie_rx1n t24 pcie_vss_30 t25 pcie_rx0p t26 pcie_rx0n t27 pcie_vss_31 t28 pcie_vss_32 t29 pcie_vss_33 t3 fanout1/gpio48 t4 nc6 t5 vddq_10 t6 vss_32 t7 tempin3/talert#/ gpio64 t8 tempin2/gpio63 t9 vss_33 u1 pciclk2 u12 vdd_8 u13 vss_34 u15 vdd_9 u17 vss_35 u18 vdd_10 u2 pciclk0 u27 pcie_vss_34 u28 pcie_pvss u29 pcie_pvdd u3 pciclk5 v1 pciclk6 v12 vss_38 v13 vdd_11 ball no. signal name v15 vss_39 v17 vdd_12 v18 vss_40 v2 pciclk3 v21 vss_41 v22 pcie_vss_35 v23 pcie_vss_36 v24 pcie_vss_37 v25 pcie_vss_38 v26 pcie_vss_39 v27 pcie_vss_40 v28 pcie_vss_41 v29 pcie_vss_42 v3 vss_36 v4 fanout2/gpio49 v5 vin0/gpio53 v6 vin3/gpio56 v7 vin7/gpio60 v8 vss_37 v9 vddq_11 w1 vss_42 w2 vddq_12 w21 vddq_14 w22 bmreq#/req5#/gpio65 w23 dprslpvr w24 nmi/lint1 w25 init# w26 intr/lint0 w27 ide_cs3# w28 ide_cs1# w29 vddq_15 w3 pciclk4 w4 fanin2/gpio52 w5 ad3/roma15 w6 vddq_13 w7 ad0/roma18 w8 ad2/roma16
?2007- 2008 advanced micro devices, inc. sb600 pin listing sb600 databook proprietary page 104 ball no. signal name w9 vss_43 y1 ad1/roma17 y2 stop# y27 ferr# y28 ide_a2 y29 vss_44 y3 ad5/roma13
?2007- 2008 advanced micro devices, inc. appendix b: revision history ati sb600 databook proprietary page 105 appendix b: revision history note: the revision number of the manual reflects eit her one of the two release states defined below: preliminary release ? revision numbers from 0.1 to 0.9. generally with incomplete information and/or information subject to change. full release ? revision numbers from 1.0 onwards. occu rring after essential elements have been reviewed, typically after tape-out. date rev. comment july 2, 2008 3.05 changed ?amd confidential? to ?proprietary? in document footers. also changed file name of the document. nov 30, 2007 3.04 updated se ction 4.1: added vdd in note 1, and added vdd vs. pcie_pvdd power sequence requirement in note 2. added chapter 11, ?thermal information.? april 20, 2007 3.03 updated section 3.5, ?usb in terface?: added note on esd protection for usb_hsdp[9:0]+ and usb_hsdm[9:0]- signals. updated section 8.4, ?rtc batte ry current consumption?: updated statement on expectancy of rtc battery life. april 11, 2007 3.02 added references to smartvolt2 corrected header of table 8- 4, ?gpio/gevent output dc characteristics.? updated table 8-6, ?rtc battery current consumption.? updated the note on heat sink in ch.9, ?power requirements.? jan 8, 2007 3.01 upda ted the following: section 3.9, ?smbus interface / gener al purpose open collector?: added note. section 3.13, ?external event / general event / general power management / general purpose open co llector?: added note 2 and see notes. section 3.19, ?power and ground?: modified note 3. ?table 4-1: sb600 power up/down sequence timing?: modified the t2 min value. section 4.1, ?power up/down sequence timing notes?: modified note 15 and 16. ?table 6-3: 14 mhz osc reference clock ac specifications?: modified the duty cycle min value. dec 19, 2006 3.00 revised general format and styles to reflect new corporate identity. raised revision number to 3.00 according to the amd scheme. updated 1.1, ?features of the sb600?: added hot plug support by sata controller (ahci mode only); removed support for thermal diode temperature sensing function. updated section 4.1, ?power up and down sequences.? updated table 6-2, ?system clock input frequency specifications?: revised specifications for 14m_os c; added ac_bitclk specification. updated table 6-3, ?14 mhz osc re ference clock ac specifications?: and table 6-4, ?48mhz usb/sio clock ac specifications?: revised clock period specifications and added clock frequency tolerance. updated table 8-2, ?dc characteristi cs for power supplies to the sb600?: added note on minimum value of vbat. updated section 10.2, ?pre ssure specification.? oct 27, 2006 1.2 updated section 4.1, ?power up and down sequences.? updated table 4.2, ?external resist or requirements and integrated pull up/down?: clarified description for feer# (leave unconnected for amd platforms). aug 25, 2006 1.1 updated sectio n 1.2, ?part number and branding?: revised branding diagram and removed part numbers for leaded parts. updated section 3.12, ?general purp ose i/o?: added notes regarding pins
?2007- 2008 advanced micro devices, inc. appendix b: revision history ati sb600 databook proprietary page 106 date rev. comment with pci rom functions and ldrg1#/gnt65#/gpio68. updated section 3.13, ?general event/??: expanded note on s3_state/gevent5#. updated section 4.1, ?power up and down sequences?: added t9a, removed t14a, and made other minor changes. added table 9-1, ?power activity under configuration 1.? aug 21, 2006 1.0 specified that pci (x bus) rom is not supported for asic revision a21 and onwards. revised section 1.1, ?features of the sb600?: added sata port multiplier support and a note on esata support. revised table 1-1, ?sb600 part nu mbers?: added part numbers for asic revision a13 and a21. revised section 3.15, ? hd audio interface?: changed i/o type to ?o? for az_bitclk, az_rst#, az_sdout, and az_sync. added section 6.3, ?system clock ac specifications.? updated section 4.1, ?power up an d down sequences?: revised some numbers and combined the original sections on power up and power down sequences into one. made ?power requirements? a separate chapter, and updated it with new numbers. june 23, 2006 0.6 updated sectio n 1.1, ?features of the sb600 ?: corrected feature list for sata ii support. updated table 4.1-1 ?sb600 power on sequence timing?: revised values for t8d and t13. added table 6-2:?sb600 system clo ck input frequency specifications.? may 9, 2006 0.5 clarified that pin a1 (vss _1) only exists on asic a11. affected the following: figure 5, sb600 ball-out assignment?, figure 27, ?sb600 package outline?; appendix a, ?pin listing.? updated section 1.1, ?features of the sb600?: restricted the lpc controller?s spi device support to 33mhz maximum. updated section 3.7, ?power m anagement/north bridge interface?: corrected pin type for sus_stat# to simply ?od,? and that of ldt_stp# [amd] to ?o?. updated table 3.20-3, ?additional st raps?: corrected pull-up rail for rtcclk strap to s5_3.3v. updated table 4.1-1, ?sb600 power on sequence timing?: added note 9 to the description of t11. april 2006 0.4 updated secti on 1.1, ?features of the sb6 00?: added that apm is not supported. updated table 4.1-1, ?sb600 power on sequence timing?: revised maximum time between sb pwr_good and ldt pg (t8d) to 48.15ms. updated table 4.2-1: ?sb600 power down timing?: revised maximum sb pwr_good fall time (t7b) to 1s. revised table 5.8-2, ?functionalit y of the general events and gpios across acpi states?: changed functionality for gpio [73:0]. april 2006 0.3 updated table 4.1-1, ? sb600 power on sequence timing?: revised values for t8c, t8d, t9, and t11; corrected label t14 to t15. updated figure 13 and table 4.2-1: ?sb600 power down timing?: added fall time for rsm_rst# (t14a). updated table 3.20-1: ?s tandard straps?: changed default value for strap on pciclk4 to that of ?0v.? updated section 3.12, ?general purpose i/o?: changed i/o type of lan_rst#/gpio13 to ?o.? updated section 3.6, ?serial ata inte rface?: added a note to the end of the table. updated table 4.4-1, ?external resist ors requirements and integrated pull up/down?: made various corrections and additions to the table. revised table 5.8-2, ?functionalit y of the general events and gpios across acpi states.? updated table 8.4.1, ?power estimate s for the sb600?: put in ?tbd? for power estimates.
?2007- 2008 advanced micro devices, inc. appendix b: revision history ati sb600 databook proprietary page 107 date rev. comment updated table 9-1.1, ?sb600 package physical dimensions?: revised minimum and maximum values of subs trate thickness (parameter ?c?). updated section 9.2, ?pressure specification?: elaborated on the specification. updated table 10.1-1, ?signals for the test controller of the sb600?: corrected ball references for test0 and test1. feb 2006 0.2 updated table 1.3.-1, ?sb600 part number?: added part numbers for asic a11, substrate revision b, and asic a12. updated section 3.1, ?a-link express ii interface?: changed description for pcie_cali. updated section 3.12, ?general pu rpose i/o?: corrected information on various pins. updated section 3.13,, ?external event / general event / general power management / general purpose open co llector?: corrected information on various pins. updated section 3.7, ?power mana gement / north bridge interface?: updated pin description for wake#/gevent8#. updated section 4.1, ?power up sequences?: put in new details and requirements. updated table 4.4-1, ?external resist or requirements and integrated pull up/down?: corrected external resistor requirement for usb_oc9#/slp_s2/gpm9# to 10k pull-down. updated section 9.1, ?physical dim ensions?: updated package diagram to show substrate rev. b; added detailed dimension figures. added section 9.2, ?pre ssure specification.? nov 2005 0.1 replaced table 5.8-3 with a reference to the rrg oct 2005 0.09 preliminary release

▲Up To Search▲

Price & Availability of 218S6ECLA13FG

	To Download 218S6ECLA13FG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .